From patchwork Tue Dec 18 18:31:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 1893441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 897653FCD4 for ; Tue, 18 Dec 2012 18:47:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72A3EE5D52 for ; Tue, 18 Dec 2012 10:47:00 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fmsmga101.fm.intel.com (mga05.intel.com [192.55.52.89]) by gabe.freedesktop.org (Postfix) with ESMTP id DC54FE63B2 for ; Tue, 18 Dec 2012 10:35:19 -0800 (PST) Received: from mail-pa0-f70.google.com ([209.85.220.70]) by mga01.intel.com with ESMTP/TLS/RC4-SHA; 18 Dec 2012 10:35:19 -0800 Received: by mail-pa0-f70.google.com with SMTP id hz11so1070327pad.9 for ; Tue, 18 Dec 2012 10:35:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=zD/gjC4woZBy4o2w6qPjuzlBeLQuagL9E3nm38v4EXw=; b=eY4XxA3n32/DdivRXIjx/9VoKRMzw7oDKqBw/e0kuf5G+yzlwg1Ca9rStHoRnWD+AB a6j1dzemOL+zy2GC9za3IarpQVdhLY8jzQbyWbG2CY8sPH5ZjFfEsf1qIpgJd31D4mRz nY7sOtlb8+EPMiFyt5KTaNCYMou8a72koFpBbMw+4kjvD/S1ytSR70Qg5Q5P7/T2FBSf L44A5oXomcwvMQrE+aYVN9xARIt+hIgRukZ63Z3pO8NDMIoTbGdqQoegm82ZWmJ3Vnzw KHW31i44fqizjKbd3MasDGxaiIWTpsIdnzxen4iDPSuVKI6dnfz2QYLog1ufrbs63SIH M8/A== X-Received: by 10.68.209.136 with SMTP id mm8mr9251258pbc.146.1355855719183; Tue, 18 Dec 2012 10:35:19 -0800 (PST) X-Received: by 10.68.209.136 with SMTP id mm8mr9251244pbc.146.1355855719105; Tue, 18 Dec 2012 10:35:19 -0800 (PST) Received: from norris.jf.intel.com ([192.55.55.41]) by mx.google.com with ESMTPS id ip8sm1552525pbc.36.2012.12.18.10.35.17 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Dec 2012 10:35:18 -0800 (PST) From: Ben Widawsky To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Dec 2012 10:31:25 -0800 Message-Id: <1355855487-20424-4-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.8.0.1 In-Reply-To: <1355855487-20424-1-git-send-email-ben@bwidawsk.net> References: <1355855487-20424-1-git-send-email-ben@bwidawsk.net> X-Gm-Message-State: ALoCoQl680hH6qX4aq2njxa3yN9ofzEgRYbEFEHfWNwWT0ztZhLDIDPZqgnWmp0H7lYrZJLDSeRjgyJXb2cjAi0yS73svFgXq2MSSB3hC7wfco1k1w8WwKaCZSn7sLGKFzPkubYi+ePBkBl7WMEcylK0Dvm8hR+tm4fQWNwPOddjIBZsaapMqYM= X-Mailman-Approved-At: Tue, 18 Dec 2012 10:45:20 -0800 Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Move even more gtt code to i915_gem_gtt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This really should have been part of the kill agp series. Signed-off-by: Ben Widawsky Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 7 ++--- drivers/gpu/drm/i915/i915_gem.c | 51 ++------------------------------ drivers/gpu/drm/i915/i915_gem_gtt.c | 59 ++++++++++++++++++++++++++++++++++--- 3 files changed, 61 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2ab476d..75003c3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1585,10 +1585,9 @@ void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); -void i915_gem_init_global_gtt(struct drm_device *dev, - unsigned long start, - unsigned long mappable_end, - unsigned long end); +void i915_gem_init_global_gtt(struct drm_device *dev); +void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, + unsigned long mappable_end, unsigned long end); int i915_gem_gtt_init(struct drm_device *dev); void i915_gem_gtt_fini(struct drm_device *dev); static inline void i915_gem_chipset_flush(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4c6f043..42b948b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -163,8 +163,8 @@ i915_gem_init_ioctl(struct drm_device *dev, void *data, return -ENODEV; mutex_lock(&dev->struct_mutex); - i915_gem_init_global_gtt(dev, args->gtt_start, - args->gtt_end, args->gtt_end); + i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, + args->gtt_end); mutex_unlock(&dev->struct_mutex); return 0; @@ -3959,58 +3959,13 @@ cleanup_render_ring: return ret; } -static bool -intel_enable_ppgtt(struct drm_device *dev) -{ - if (i915_enable_ppgtt >= 0) - return i915_enable_ppgtt; - -#ifdef CONFIG_INTEL_IOMMU - /* Disable ppgtt on SNB if VT-d is on. */ - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) - return false; -#endif - - return true; -} - int i915_gem_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - unsigned long gtt_size, mappable_size; int ret; - gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; - mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; - mutex_lock(&dev->struct_mutex); - if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { - /* PPGTT pdes are stolen from global gtt ptes, so shrink the - * aperture accordingly when using aliasing ppgtt. */ - gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; - - i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); - - ret = i915_gem_init_aliasing_ppgtt(dev); - if (ret) { - mutex_unlock(&dev->struct_mutex); - return ret; - } - } else { - /* Let GEM Manage all of the aperture. - * - * However, leave one page at the end still bound to the scratch - * page. There are a number of places where the hardware - * apparently prefetches past the end of the object, and we've - * seen multiple hangs with the GPU head pointer stuck in a - * batchbuffer bound at the last page of the aperture. One page - * should be enough to keep any prefetching inside of the - * aperture. - */ - i915_gem_init_global_gtt(dev, 0, mappable_size, - gtt_size); - } - + i915_gem_init_global_gtt(dev); ret = i915_gem_init_hw(dev); mutex_unlock(&dev->struct_mutex); if (ret) { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index b699a04..fc3c08a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -525,10 +525,10 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node, } } -void i915_gem_init_global_gtt(struct drm_device *dev, - unsigned long start, - unsigned long mappable_end, - unsigned long end) +void i915_gem_setup_global_gtt(struct drm_device *dev, + unsigned long start, + unsigned long mappable_end, + unsigned long end) { drm_i915_private_t *dev_priv = dev->dev_private; struct drm_mm_node *entry; @@ -573,6 +573,57 @@ void i915_gem_init_global_gtt(struct drm_device *dev, i915_ggtt_clear_range(dev, end / PAGE_SIZE - 1, 1); } +static bool +intel_enable_ppgtt(struct drm_device *dev) +{ + if (i915_enable_ppgtt >= 0) + return i915_enable_ppgtt; + +#ifdef CONFIG_INTEL_IOMMU + /* Disable ppgtt on SNB if VT-d is on. */ + if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) + return false; +#endif + + return true; +} + +void i915_gem_init_global_gtt(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + unsigned long gtt_size, mappable_size; + int ret; + + gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; + mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; + + if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { + /* PPGTT pdes are stolen from global gtt ptes, so shrink the + * aperture accordingly when using aliasing ppgtt. */ + gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; + + i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); + + ret = i915_gem_init_aliasing_ppgtt(dev); + if (ret) { + mutex_unlock(&dev->struct_mutex); + return; + } + } else { + /* Let GEM Manage all of the aperture. + * + * However, leave one page at the end still bound to the scratch + * page. There are a number of places where the hardware + * apparently prefetches past the end of the object, and we've + * seen multiple hangs with the GPU head pointer stuck in a + * batchbuffer bound at the last page of the aperture. One page + * should be enough to keep any prefetching inside of the + * aperture. + */ + i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); + } +} + static int setup_scratch_page(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private;