| Message ID | 1357588059-6631-4-git-send-email-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Jan 07, 2013 at 09:47:35PM +0200, Imre Deak wrote: > Signed-off-by: Imre Deak <imre.deak@intel.com> I've applied patches 1-3 from this series, since they look like nice cleanups. Like discussed on irc, I'm not sold on the later ones since I don't see a clear upside ... -Daniel > --- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/i915_gem.c | 2 +- > drivers/gpu/drm/i915/i915_gem_tiling.c | 13 +------------ > 3 files changed, 4 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 154323a..3b73615 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1566,6 +1566,8 @@ void i915_gem_free_all_phys_object(struct drm_device *dev); > void i915_gem_release(struct drm_device *dev, struct drm_file *file); > > uint32_t > +i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); > +uint32_t > i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, > int tiling_mode, bool fenced); > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 5e00dc1..aa6653d 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -1435,7 +1435,7 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj) > obj->fault_mappable = false; > } > > -static uint32_t > +uint32_t > i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) > { > uint32_t gtt_size; > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c > index cb71ded..e76f0d8 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -272,18 +272,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) > return false; > } > > - /* > - * Previous chips need to be aligned to the size of the smallest > - * fence register that can contain the object. > - */ > - if (INTEL_INFO(obj->base.dev)->gen == 3) > - size = 1024*1024; > - else > - size = 512*1024; > - > - while (size < obj->base.size) > - size <<= 1; > - > + size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); > if (obj->gtt_space->size != size) > return false; > > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, 2013-01-14 at 17:14 +0100, Daniel Vetter wrote: > On Mon, Jan 07, 2013 at 09:47:35PM +0200, Imre Deak wrote: > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > I've applied patches 1-3 from this series, since they look like nice > cleanups. Like discussed on irc, I'm not sold on the later ones since I > don't see a clear upside ... I understood there are other ways to corrupt buffers than what this patch would fix, so I agree that it's not a security fix. I would still argue that eliminating this particular way makes things more robust against obscure application bugs. --Imre > -Daniel > > --- > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > drivers/gpu/drm/i915/i915_gem.c | 2 +- > > drivers/gpu/drm/i915/i915_gem_tiling.c | 13 +------------ > > 3 files changed, 4 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 154323a..3b73615 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1566,6 +1566,8 @@ void i915_gem_free_all_phys_object(struct drm_device *dev); > > void i915_gem_release(struct drm_device *dev, struct drm_file *file); > > > > uint32_t > > +i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); > > +uint32_t > > i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, > > int tiling_mode, bool fenced); > > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > > index 5e00dc1..aa6653d 100644 > > --- a/drivers/gpu/drm/i915/i915_gem.c > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > @@ -1435,7 +1435,7 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj) > > obj->fault_mappable = false; > > } > > > > -static uint32_t > > +uint32_t > > i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) > > { > > uint32_t gtt_size; > > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c > > index cb71ded..e76f0d8 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > > @@ -272,18 +272,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) > > return false; > > } > > > > - /* > > - * Previous chips need to be aligned to the size of the smallest > > - * fence register that can contain the object. > > - */ > > - if (INTEL_INFO(obj->base.dev)->gen == 3) > > - size = 1024*1024; > > - else > > - size = 512*1024; > > - > > - while (size < obj->base.size) > > - size <<= 1; > > - > > + size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); > > if (obj->gtt_space->size != size) > > return false; > > > > -- > > 1.7.10.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 154323a..3b73615 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1566,6 +1566,8 @@ void i915_gem_free_all_phys_object(struct drm_device *dev); void i915_gem_release(struct drm_device *dev, struct drm_file *file); uint32_t +i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); +uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, int tiling_mode, bool fenced); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5e00dc1..aa6653d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1435,7 +1435,7 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj) obj->fault_mappable = false; } -static uint32_t +uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) { uint32_t gtt_size; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index cb71ded..e76f0d8 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -272,18 +272,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) return false; } - /* - * Previous chips need to be aligned to the size of the smallest - * fence register that can contain the object. - */ - if (INTEL_INFO(obj->base.dev)->gen == 3) - size = 1024*1024; - else - size = 512*1024; - - while (size < obj->base.size) - size <<= 1; - + size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); if (obj->gtt_space->size != size) return false;
Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_tiling.c | 13 +------------ 3 files changed, 4 insertions(+), 13 deletions(-)