@@ -256,6 +256,7 @@ static bool
i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
{
u32 size;
+ u32 align;
if (tiling_mode == I915_TILING_NONE)
return true;
@@ -275,7 +276,10 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
if (obj->gtt_space->size != size)
return false;
- if (obj->gtt_offset & (size - 1))
+ align = i915_gem_get_gtt_alignment(obj->base.dev, obj->base.size,
+ tiling_mode, true);
+
+ if (obj->gtt_offset & (align - 1))
return false;
return true;
So far we used the object size for alignment check, since this matched the actual alignment requirement. An upcoming patch will introduce linear and physical fenced sizes making this connection less clear, so use instead the get-alignment function explicitly. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_gem_tiling.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)