From patchwork Fri Jan 11 19:57:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 1967171 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 95536DF2A2 for ; Fri, 11 Jan 2013 20:06:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9922EE6C7F for ; Fri, 11 Jan 2013 12:06:12 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ye0-f177.google.com (mail-ye0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 376234BD2E for ; Fri, 11 Jan 2013 12:01:18 -0800 (PST) Received: by mail-ye0-f177.google.com with SMTP id m14so402552yen.22 for ; Fri, 11 Jan 2013 12:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=mnWi7anHCuM1cere+BCO1QyTM6JGuLPoK8oVQjkx0Vk=; b=G6iMxr0NvTJCKGuykZv3NfzJmMQIrbar00d1bgw7JaGg5wa+3Wz4ewlkNqjqb6v7GY NKWLdy6M1OtlK8eTKR9pj+AvALfXQrbQj0yZtWFUuFd0uwKleDrvzu4wKLzDLaubidEw mwjxu872dpQ43Do7S+LghVOHrhrzVZfFJm68yVpVlqtk8QSbd9AeMtdOiEvzAIXADYJA 5tBwE8BXCa25iMoLtOpV3RoLFeSK40RiZPNg3VjajhgEBf9zphdmiZKkxKNoL/pCIUCv CA/y8RUPoMy1saRSAoDB62n/C+0GnZ61qne06dUYkQnBhzYTOT5NAeMiKb11i8kfYB6v Kqjw== X-Received: by 10.101.136.11 with SMTP id o11mr20688952ann.26.1357934477476; Fri, 11 Jan 2013 12:01:17 -0800 (PST) Received: from localhost.localdomain ([189.0.16.214]) by mx.google.com with ESMTPS id y17sm4630713ang.12.2013.01.11.12.00.08 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 11 Jan 2013 12:01:16 -0800 (PST) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Jan 2013 17:57:50 -0200 Message-Id: <1357934277-3300-2-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1357934277-3300-1-git-send-email-rodrigo.vivi@gmail.com> References: <1357934277-3300-1-git-send-email-rodrigo.vivi@gmail.com> Cc: Sateesh Kavuri Subject: [Intel-gfx] [PATCH 1/8] drm/i915: Added eDP PSR registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Shobhit Kumar v2: Add support for psr perfromance counter register and corrected register names to reflect they are PSR registers. Also added bit definitions for the registers v3: Add missing CDCLK_FREQ register needed for PSR enabling. Signed-off-by: Sateesh Kavuri Signed-off-by: Shobhit Kumar Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5b3020f..61de724 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1561,6 +1561,40 @@ #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) +/* HSW eDP PSR registers */ +#define EDP_PSR_CTL 0x64800 +#define EDP_PSR_ENABLE (1<<31) +#define EDP_PSR_LINK_DISABLE (0<<27) +#define EDP_PSR_LINK_STANDBY (1<<27) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) +#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 +#define EDP_PSR_SKIP_AUX_EXIT (1<<12) +#define EDP_PSR_TP1_TP2_SEL (0<<11) +#define EDP_PSR_TP1_TP3_SEL (1<<11) +#define EDP_PSR_TP2_TP3_TIME_500us (0<<8) +#define EDP_PSR_TP2_TP3_TIME_100us (1<<8) +#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) +#define EDP_PSR_TP2_TP3_TIME_0us (3<<8) +#define EDP_PSR_TP1_TIME_500us (0<<4) +#define EDP_PSR_TP1_TIME_100us (1<<4) +#define EDP_PSR_TP1_TIME_2500us (2<<4) +#define EDP_PSR_TP1_TIME_0us (3<<4) +#define EDP_PSR_IDLE_FRAME_SHIFT 0 + +#define EDP_PSR_AUX_CTL 0x64810 +#define EDP_PSR_AUX_DATA1 0x64814 +#define EDP_PSR_AUX_DATA2 0x64818 +#define EDP_PSR_AUX_DATA3 0x6481c +#define EDP_PSR_AUX_DATA4 0x64820 +#define EDP_PSR_AUX_DATA5 0x64824 +#define EDP_PSR_STATUS_CTL 0x64840 +#define EDP_PSR_STATUS_MASK (7<<29) +#define EDP_PSR_PERF_CNT 0x64844 + /* VGA port control */ #define ADPA 0x61100 #define PCH_ADPA 0xe1100 @@ -1822,6 +1856,16 @@ #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) +#define VIDEO_DIP_CTL_EDP 0x6F200 + #define VIDEOP_DIP_VSC (1<<20) + #define VIDEOP_DIP_GCP (1<<16) + #define VIDEOP_DIP_AVI (1<<12) + #define VIDEOP_DIP_VS (1<<8) + #define VIDEOP_DIP_GMP (1<<4) + #define VIDEOP_DIP_SPD (1<<0) + +#define VIDEO_DIP_VSC_DATA_EDP 0x6F320 + /* Panel power sequencing */ #define PP_STATUS 0x61200 #define PP_ON (1 << 31) @@ -3463,6 +3507,9 @@ #define HSW_FUSE_STRAP 0x42014 #define HSW_CDCLK_LIMIT (1 << 24) +#define CDCLK_FREQ 0x46200 +#define CDCLK_FREQ_MASK 0x3ff + /* PCH */ /* south display engine interrupt: IBX */