From patchwork Thu Jan 24 13:29:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 2032071 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 14AD1DF264 for ; Thu, 24 Jan 2013 13:45:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F324BE6BF3 for ; Thu, 24 Jan 2013 05:45:56 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F879E6BBC for ; Thu, 24 Jan 2013 05:31:44 -0800 (PST) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 24 Jan 2013 05:31:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,529,1355126400"; d="scan'208";a="247906615" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.168]) by azsmga001.ch.intel.com with SMTP; 24 Jan 2013 05:31:42 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 24 Jan 2013 15:31:41 +0200 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Jan 2013 15:29:54 +0200 Message-Id: <1359034198-19678-30-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.7.12.4 In-Reply-To: <1359034198-19678-1-git-send-email-ville.syrjala@linux.intel.com> References: <1359034198-19678-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 29/33] drm/i915: VGA registers need an offset on VLV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Ville Syrjälä Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c149426..75b46c8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -133,25 +133,25 @@ /* VGA stuff */ -#define VGA_ST01_MDA 0x3ba -#define VGA_ST01_CGA 0x3da +#define VGA_ST01_MDA (dev_priv->info->display_mmio_offset + 0x3ba) +#define VGA_ST01_CGA (dev_priv->info->display_mmio_offset + 0x3da) -#define VGA_MSR_WRITE 0x3c2 -#define VGA_MSR_READ 0x3cc +#define VGA_MSR_WRITE (dev_priv->info->display_mmio_offset + 0x3c2) +#define VGA_MSR_READ (dev_priv->info->display_mmio_offset + 0x3cc) #define VGA_MSR_MEM_EN (1<<1) #define VGA_MSR_CGA_MODE (1<<0) -#define VGA_SR_INDEX 0x3c4 +#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4) #define SR01 1 -#define VGA_SR_DATA 0x3c5 +#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5) -#define VGA_AR_INDEX 0x3c0 +#define VGA_AR_INDEX (dev_priv->info->display_mmio_offset + 0x3c0) #define VGA_AR_VID_EN (1<<5) -#define VGA_AR_DATA_WRITE 0x3c0 -#define VGA_AR_DATA_READ 0x3c1 +#define VGA_AR_DATA_WRITE (dev_priv->info->display_mmio_offset + 0x3c0) +#define VGA_AR_DATA_READ (dev_priv->info->display_mmio_offset + 0x3c1) -#define VGA_GR_INDEX 0x3ce -#define VGA_GR_DATA 0x3cf +#define VGA_GR_INDEX (dev_priv->info->display_mmio_offset + 0x3ce) +#define VGA_GR_DATA (dev_priv->info->display_mmio_offset + 0x3cf) /* GR05 */ #define VGA_GR_MEM_READ_MODE_SHIFT 3 #define VGA_GR_MEM_READ_MODE_PLANE 1 @@ -163,15 +163,15 @@ #define VGA_GR_MEM_B0000_B7FFF 2 #define VGA_GR_MEM_B0000_BFFFF 3 -#define VGA_DACMASK 0x3c6 -#define VGA_DACRX 0x3c7 -#define VGA_DACWX 0x3c8 -#define VGA_DACDATA 0x3c9 +#define VGA_DACMASK (dev_priv->info->display_mmio_offset + 0x3c6) +#define VGA_DACRX (dev_priv->info->display_mmio_offset + 0x3c7) +#define VGA_DACWX (dev_priv->info->display_mmio_offset + 0x3c8) +#define VGA_DACDATA (dev_priv->info->display_mmio_offset + 0x3c9) -#define VGA_CR_INDEX_MDA 0x3b4 -#define VGA_CR_DATA_MDA 0x3b5 -#define VGA_CR_INDEX_CGA 0x3d4 -#define VGA_CR_DATA_CGA 0x3d5 +#define VGA_CR_INDEX_MDA (dev_priv->info->display_mmio_offset + 0x3b4) +#define VGA_CR_DATA_MDA (dev_priv->info->display_mmio_offset + 0x3b5) +#define VGA_CR_INDEX_CGA (dev_priv->info->display_mmio_offset + 0x3d4) +#define VGA_CR_DATA_CGA (dev_priv->info->display_mmio_offset + 0x3d5) /* * Memory interface instructions used by the kernel