From patchwork Thu Jan 24 15:50:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2033301 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 23A49DF264 for ; Thu, 24 Jan 2013 16:03:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27046E6C63 for ; Thu, 24 Jan 2013 08:03:26 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 56768E5F82 for ; Thu, 24 Jan 2013 08:00:37 -0800 (PST) Received: by mail-wg0-f43.google.com with SMTP id e12so4873955wge.22 for ; Thu, 24 Jan 2013 08:00:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=/MSa5gk9+ptpT2vwYpN/RL4r4JD8+B10iPSY6k3uV2c=; b=P5f1LdQFHrDULvWbCLUJzZkvsKFEhJqVUJQ1giQMvKmmHcvnyFQVf/Gb84OUtrnU2J DRAljwfAeKY48MrA1M/Zb1B8ER1JYaMWzuEnKoX7cuYMwAw4Mdc+y7o6cdyxPh8BroX1 FN4y5nDhUyJqqZQNJsxqmkwY/ebk6MXHCaW/k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=/MSa5gk9+ptpT2vwYpN/RL4r4JD8+B10iPSY6k3uV2c=; b=R78qpLkacpsUDNMnZvYjtBNB1uJ23sJiGBQhdqQd/412slPf+dnpz3WZ3s4CpsN+EK Sn8teouVNBB0D1G6w74/sX06w4LWyjEztgQH+WevYlspVsrf1aINNsMLzPBODUK2xVei mKrJinGu2GwHQvjp3cgAu2v1dZqFqoopb4dDovkyI+JqZcGjNHXsyY/naW7CjmthmuXF ouvRrDejkLZm9fDl6wXz/jFS6zTquateFtMh0CEQMhKr15XWidY7UTyzmIw0K+5T+N2N Xbl5EVI3DpJxE4wOSTznn8xjMv56wgOkLKlLUOrEjMCYXxQeRL1L9UO2R/Qu9PmSLllg ZY1A== X-Received: by 10.180.80.230 with SMTP id u6mr3900647wix.20.1359043236355; Thu, 24 Jan 2013 08:00:36 -0800 (PST) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id bd7sm3191371wib.8.2013.01.24.08.00.35 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 24 Jan 2013 08:00:35 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 24 Jan 2013 16:50:12 +0100 Message-Id: <1359042615-30362-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1359042615-30362-1-git-send-email-daniel.vetter@ffwll.ch> References: <1359042615-30362-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQnWUj/FmiPZ7Zbb4i4M0HVdkJNuqEM57AS848VWEtwNuCNAiS2AaVR8auoX1T8hnYx//mL0 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 1/4] drm/i915: vfuncs for gtt_clear_range/insert_entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We have a few too many differences between platforms here, so finally take the prepared abstraction and run with it. A few smaller changes are required to get things into shape: - Move i915_cache_level up since we need it in the gt funcs. - Split up i915_ggtt_clear_range and move the two functions down to where the relevant insert_entries functions are. - Adjust a few function parameter lists. Now we have 2 functions which deal with the gen6+ global gtt (gen6_ggtt_ prefix) and 2 functions which deal with the legacy gtt code in the intel-gtt.c fake agp driver (i915_ggtt_ prefix). Init is still a bit a mess, but honestly I don't care about that. One thing I've thought about while deciding on the exact interfaces is a flag parameter for ->clear_range: We could use that to decide between writing invalid pte entries or scratch pte entries. In case we ever get around to fixing all our bugs which currently prevent us from filling the gtt with empty ptes for the truly unused ranges ... Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 21 +++++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 121 ++++++++++++++++++++---------------- 2 files changed, 83 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0a798ee..5e224af 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -308,9 +308,24 @@ struct drm_i915_display_funcs { /* pll clock increase/decrease */ }; +enum i915_cache_level { + I915_CACHE_NONE = 0, + I915_CACHE_LLC, + I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ +}; + struct drm_i915_gt_funcs { void (*force_wake_get)(struct drm_i915_private *dev_priv); void (*force_wake_put)(struct drm_i915_private *dev_priv); + + /* global gtt ops */ + void (*gtt_clear_range)(struct drm_device *dev, + unsigned int first_entry, + unsigned int num_entries); + void (*gtt_insert_entries)(struct drm_device *dev, + struct sg_table *st, + unsigned int pg_start, + enum i915_cache_level cache_level); }; #define DEV_INFO_FLAGS \ @@ -1025,12 +1040,6 @@ enum hdmi_force_audio { HDMI_AUDIO_ON, /* force turn on HDMI audio */ }; -enum i915_cache_level { - I915_CACHE_NONE = 0, - I915_CACHE_LLC, - I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ -}; - #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) struct drm_i915_gem_object_ops { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a0ba4a9..1698d63 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -367,40 +367,14 @@ static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) dev_priv->mm.interruptible = interruptible; } -static void i915_ggtt_clear_range(struct drm_device *dev, - unsigned first_entry, - unsigned num_entries) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - gtt_pte_t scratch_pte; - gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; - const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry; - int i; - - if (INTEL_INFO(dev)->gen < 6) { - intel_gtt_clear_range(first_entry, num_entries); - return; - } - - if (WARN(num_entries > max_entries, - "First entry = %d; Num entries = %d (max=%d)\n", - first_entry, num_entries, max_entries)) - num_entries = max_entries; - - scratch_pte = pte_encode(dev, dev_priv->gtt.scratch_page_dma, I915_CACHE_LLC); - for (i = 0; i < num_entries; i++) - iowrite32(scratch_pte, >t_base[i]); - readl(gtt_base); -} - void i915_gem_restore_gtt_mappings(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj; /* First fill our portion of the GTT with scratch pages */ - i915_ggtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, - dev_priv->gtt.total / PAGE_SIZE); + dev_priv->gt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, + dev_priv->gtt.total / PAGE_SIZE); list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { i915_gem_clflush_object(obj); @@ -429,15 +403,13 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) * within the global GTT as well as accessible by the GPU through the GMADR * mapped BAR (dev_priv->mm.gtt->gtt). */ -static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj, - enum i915_cache_level level) +static void gen6_ggtt_insert_entries(struct drm_device *dev, + struct sg_table *st, + unsigned int first_entry, + enum i915_cache_level level) { - struct drm_device *dev = obj->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct sg_table *st = obj->pages; struct scatterlist *sg = st->sgl; - const int first_entry = obj->gtt_space->start >> PAGE_SHIFT; - const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry; gtt_pte_t __iomem *gtt_entries = (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; int unused, i = 0; @@ -453,9 +425,6 @@ static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj, } } - BUG_ON(i > max_entries); - BUG_ON(i != obj->base.size / PAGE_SIZE); - /* XXX: This serves as a posting read to make sure that the PTE has * actually been updated. There is some concern that even though * registers and PTEs are within the same BAR that they are potentially @@ -473,28 +442,69 @@ static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj, POSTING_READ(GFX_FLSH_CNTL_GEN6); } +static void gen6_ggtt_clear_range(struct drm_device *dev, + unsigned int first_entry, + unsigned int num_entries) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + gtt_pte_t scratch_pte; + gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; + const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry; + int i; + + if (WARN(num_entries > max_entries, + "First entry = %d; Num entries = %d (max=%d)\n", + first_entry, num_entries, max_entries)) + num_entries = max_entries; + + scratch_pte = pte_encode(dev, dev_priv->gtt.scratch_page_dma, I915_CACHE_LLC); + for (i = 0; i < num_entries; i++) + iowrite32(scratch_pte, >t_base[i]); + readl(gtt_base); +} + + +static void i915_ggtt_insert_entries(struct drm_device *dev, + struct sg_table *st, + unsigned int pg_start, + enum i915_cache_level cache_level) +{ + unsigned int flags = (cache_level == I915_CACHE_NONE) ? + AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; + + intel_gtt_insert_sg_entries(st, pg_start, flags); + +} + +static void i915_ggtt_clear_range(struct drm_device *dev, + unsigned int first_entry, + unsigned int num_entries) +{ + intel_gtt_clear_range(first_entry, num_entries); +} + + void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, enum i915_cache_level cache_level) { struct drm_device *dev = obj->base.dev; - if (INTEL_INFO(dev)->gen < 6) { - unsigned int flags = (cache_level == I915_CACHE_NONE) ? - AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; - intel_gtt_insert_sg_entries(obj->pages, - obj->gtt_space->start >> PAGE_SHIFT, - flags); - } else { - gen6_ggtt_bind_object(obj, cache_level); - } + struct drm_i915_private *dev_priv = dev->dev_private; + + dev_priv->gt.gtt_insert_entries(dev, obj->pages, + obj->gtt_space->start >> PAGE_SHIFT, + cache_level); obj->has_global_gtt_mapping = 1; } void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) { - i915_ggtt_clear_range(obj->base.dev, - obj->gtt_space->start >> PAGE_SHIFT, - obj->base.size >> PAGE_SHIFT); + struct drm_device *dev = obj->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + dev_priv->gt.gtt_clear_range(obj->base.dev, + obj->gtt_space->start >> PAGE_SHIFT, + obj->base.size >> PAGE_SHIFT); obj->has_global_gtt_mapping = 0; } @@ -570,13 +580,12 @@ void i915_gem_setup_global_gtt(struct drm_device *dev, hole_start, hole_end) { DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", hole_start, hole_end); - i915_ggtt_clear_range(dev, - hole_start / PAGE_SIZE, - (hole_end-hole_start) / PAGE_SIZE); + dev_priv->gt.gtt_clear_range(dev, hole_start / PAGE_SIZE, + (hole_end-hole_start) / PAGE_SIZE); } /* And finally clear the reserved guard page */ - i915_ggtt_clear_range(dev, end / PAGE_SIZE - 1, 1); + dev_priv->gt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); } static bool @@ -718,6 +727,9 @@ int i915_gem_gtt_init(struct drm_device *dev) dev_priv->gtt.do_idle_maps = needs_idle_maps(dev); + dev_priv->gt.gtt_clear_range = i915_ggtt_clear_range; + dev_priv->gt.gtt_insert_entries = i915_ggtt_insert_entries; + return 0; } @@ -771,6 +783,9 @@ int i915_gem_gtt_init(struct drm_device *dev) DRM_DEBUG_DRIVER("GMADR size = %ldM\n", dev_priv->gtt.mappable_end >> 20); DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20); + dev_priv->gt.gtt_clear_range = gen6_ggtt_clear_range; + dev_priv->gt.gtt_insert_entries = gen6_ggtt_insert_entries; + return 0; err_out: