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[5/9] drm/i915: Include display_mmio_offset in sequencer index/data registers

Message ID 1359143089-14284-6-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Jan. 25, 2013, 7:44 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

SR01 needs to be touched to disable VGA on non-UMS setups too.
So the sequencer registers need to include the appripriate offset
on VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Daniel Vetter Jan. 26, 2013, 4:43 p.m. UTC | #1 
On Fri, Jan 25, 2013 at 09:44:45PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> SR01 needs to be touched to disable VGA on non-UMS setups too.
> So the sequencer registers need to include the appripriate offset
> on VLV.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I've applied patches up to this one. The vga_cntrl one needs the
safe/restore patches applied first, which is awaiting a bit of review. And
I think before I merge the patch to finally kill IS_DISPLAYREG a few days
of testing would be good.

Thanks for doing this.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 213ff6c..9f4305f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -141,9 +141,15 @@ 
 #define   VGA_MSR_MEM_EN (1<<1)
 #define   VGA_MSR_CGA_MODE (1<<0)
 
-#define VGA_SR_INDEX 0x3c4
+/*
+ * SR01 is the only VGA register touched on non-UMS setups.
+ * VLV doesn't do UMS, so the sequencer index/data registers
+ * are the only VGA registers which need to include
+ * display_mmio_offset.
+ */
+#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
 #define SR01			1
-#define VGA_SR_DATA 0x3c5
+#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
 
 #define VGA_AR_INDEX 0x3c0
 #define   VGA_AR_VID_EN (1<<5)