From patchwork Fri Jan 25 20:57:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 2048401 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 29F14DF23E for ; Fri, 25 Jan 2013 23:27:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F2955E6676 for ; Fri, 25 Jan 2013 15:27:32 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f176.google.com (mail-gh0-f176.google.com [209.85.160.176]) by gabe.freedesktop.org (Postfix) with ESMTP id F3755E6011 for ; Fri, 25 Jan 2013 12:58:01 -0800 (PST) Received: by mail-gh0-f176.google.com with SMTP id f16so130220ghb.7 for ; Fri, 25 Jan 2013 12:58:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=yjM/kmNf1TQrGDQCors9uYdwJVSzkXEQsue08yDenUo=; b=eM5iQr1RKgoUx/WM+Qidw4uvlGhCszp3FcG01BsZBllubQWPWwHFBfFFpN8DHa4WzM Tytk9K9D6bmOcp8nDGLUEdlwsK8UfCO8+4o58hLE5xpOOtGa64h1CZnPlFUuU87Q0jvP dV3xShsELkRHnRhfcOlp8oYar+wcJdGR3jdkKVC46foYVIZxGU+vDiqOayisolg2MyP9 yS7ThExeFiUoItIRtR2Ln7Ahwu/IUGLAZSgHqVNcPS9fxCiqRsxR2XLXnli7l2CHK2S6 oxuv5/u90YesfGriDT8R9IS+14Z0PQ7jdESnVSS1ZjpO+l6p9s1dCxyTPd5WfTfGgM7i ZLkQ== X-Received: by 10.236.131.9 with SMTP id l9mr7703974yhi.93.1359147481357; Fri, 25 Jan 2013 12:58:01 -0800 (PST) Received: from vicky.domain.invalid ([177.42.13.174]) by mx.google.com with ESMTPS id k63sm2088659yhj.20.2013.01.25.12.57.59 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 25 Jan 2013 12:58:00 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 25 Jan 2013 18:57:37 -0200 Message-Id: <1359147462-3902-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1359147462-3902-1-git-send-email-przanoni@gmail.com> References: <1359147462-3902-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 2/7] drm/i915: use FPGA_DBG for the "unclaimed register" checks X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni We plan to treat GEN7_ERR_INT as an interrupt, so use this register for the checks inside I915_WRITE. This way we can have the best of both worlds: the error message with a register address and the interrupt. V2: Split in 2 patches: one for the macro, one for changing the register, as requested by Ben. Signed-off-by: Paulo Zanoni Reviewed-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_drv.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ae0a55a..f47de4d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1226,16 +1226,16 @@ ilk_dummy_write(struct drm_i915_private *dev_priv) #define UNCLAIMED_REG_CLEAR(dev_priv, reg) \ if (IS_HASWELL(dev_priv->dev) && \ - (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ + (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { \ DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ - I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ + I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); \ } #define UNCLAIMED_REG_CHECK(dev_priv, reg) \ if (IS_HASWELL(dev_priv->dev) && \ - (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ + (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { \ DRM_ERROR("Unclaimed write to %x\n", reg); \ - writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ + I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); \ } #define __i915_read(x, y) \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 15c15a5..ee30fb9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -515,6 +515,9 @@ #define GEN7_ERR_INT 0x44040 #define ERR_INT_MMIO_UNCLAIMED (1<<13) +#define FPGA_DBG 0x42300 +#define FPGA_DBG_RM_NOCLAIM (1<<31) + /* GM45+ chicken bits -- debug workaround bits that may be required * for various sorts of correct behavior. The top 16 bits of each are * the enables for writing to the corresponding low bit.