From patchwork Mon Jan 28 20:36:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 2058341 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 877ED3FD49 for ; Mon, 28 Jan 2013 20:36:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 86250E6143 for ; Mon, 28 Jan 2013 12:36:41 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from shiva.chad-versace.us (209-20-75-48.static.cloud-ips.com [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id BAEAFE60F0 for ; Mon, 28 Jan 2013 12:35:09 -0800 (PST) Received: by shiva.chad-versace.us (Postfix, from userid 1005) id 41E8088121; Mon, 28 Jan 2013 20:38:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on shiva.chad-versace.us X-Spam-Level: X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.3.2 Received: from lundgren.jf.intel.com (unknown [134.134.139.76]) by shiva.chad-versace.us (Postfix) with ESMTPSA id 40FED880FF; Mon, 28 Jan 2013 20:37:57 +0000 (UTC) From: Ben Widawsky To: Intel GFX Date: Mon, 28 Jan 2013 12:36:34 -0800 Message-Id: <1359405394-23465-1-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1359160867-780-6-git-send-email-ben@bwidawsk.net> References: <1359160867-780-6-git-send-email-ben@bwidawsk.net> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Dynamically calculate dclv X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Directory CacheLine Valid controls which PDEs are held in the directory cache. Each bit represents 16 PDEs (16 PDEs at 4 bytes per entry is 1 cacheline, and therefore, almost makes sense). Since we can now have an aliasing PPGTT which isn't 2GB, theoretically, we should also modify the DCLV value to fit accordingly. v2: Add part of this commit message to the code as a comment (Jani) Reviewed-by: Ben Widawsky Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++-- drivers/gpu/drm/i915/i915_reg.h | 1 - 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 7d8c2e5..2fc866a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -344,11 +344,14 @@ void i915_gem_init_ppgtt(struct drm_device *dev) } for_each_ring(ring, dev_priv, i) { + /* Directory CacheLine Valid controls which PDEs are held in the + * directory cache. Each bit represents 16 PDEs */ + uint64_t dclv = ppgtt->mapped_size >> 26; + dclv = (1ULL << dclv) - 1; if (INTEL_INFO(dev)->gen >= 7) I915_WRITE(RING_MODE_GEN7(ring), _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); - - I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); + I915_WRITE(RING_PP_DIR_DCLV(ring), dclv); I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0c89cf5..c5ac375 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -117,7 +117,6 @@ #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) -#define PP_DIR_DCLV_2G 0xffffffff #define GAM_ECOCHK 0x4090 #define ECOCHK_SNB_BIT (1<<10)