From patchwork Tue Jan 29 18:35:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 2063561 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 709773FDD1 for ; Tue, 29 Jan 2013 18:36:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4BB33E5DE4 for ; Tue, 29 Jan 2013 10:36:42 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by gabe.freedesktop.org (Postfix) with ESMTP id 84ED3E60F8 for ; Tue, 29 Jan 2013 10:35:48 -0800 (PST) Received: by mail-gh0-f180.google.com with SMTP id f13so119327ghb.39 for ; Tue, 29 Jan 2013 10:35:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=2Uo5Xo/1h/JmA6E/TowGrQg3eZ92PV4CBWwpgGS0v2U=; b=VfuNTBbSTDHIJAbgEu65KbKxDHVu7fjecgkARQKrS/QEG7h/xDvLKiJy1ueL8GHeEI zIwwjmjde+Z3uFHUaMC3M+btdVSbHVMqSrNjS7VNm1vd1h9Dj8xcpol6xeLWRJQAyYrH vVp7U3E2j1gpjRdZcoAdVTYY8tGbYXSkMgzL71UowAyK+bC/v8tN0Kx6TR/15CnDDLMe 5ZwKlhJUqmlBVqiJSalOwNEUYkIL1uktJaWTmn4avLt5fHUJ7mpRGIC703ihJ1Q1eCcb 0pWsy/B/okQIoS6CP7NShp7vEh3pnHaXyLC7/5RqJp3srYWtPvvSYKZvuBzj57IbXn7o BAYQ== X-Received: by 10.236.149.146 with SMTP id x18mr2310049yhj.29.1359484548039; Tue, 29 Jan 2013 10:35:48 -0800 (PST) Received: from vicky.domain.invalid ([177.132.64.67]) by mx.google.com with ESMTPS id d30sm14404437yhc.4.2013.01.29.10.35.46 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 29 Jan 2013 10:35:47 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 29 Jan 2013 16:35:20 -0200 Message-Id: <1359484520-3577-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1359484520-3577-1-git-send-email-przanoni@gmail.com> References: <1359484520-3577-1-git-send-email-przanoni@gmail.com> Cc: Daniel Vetter , Paulo Zanoni Subject: [Intel-gfx] [PATCH 3/3] drm/i915: dynamic Haswell display power well support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Daniel Vetter We can disable (almost) all the display hw if we only use pipe A, with the integrated edp transcoder on port A. Because we don't set the cpu transcoder that early (yet), we need to help us with a trick to simply check for any edp encoders. v2: Paulo Zanoni pointed out that we also need to configure the eDP cpu transcoder correctly. v3: Made by Paulo Zanoni - Rebase patch to be on top of "fix intel_init_power_wells" patch - Fix typos - Fix a small bug by adding a "connectors_active" check - Restore the initial code that unconditionally enables the power well when taking over from the BIOS v4: Made by Paulo Zanoni - One more typo spotted by Jani Nikula v5: Made by Paulo Zanoni - Rebase Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 8 +++++++- drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) I know we might not want to apply this right now, but at least there's an updated version on the list :) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 33b9112..cedf4ab 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -988,7 +988,13 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) if (cpu_transcoder == TRANSCODER_EDP) { switch (pipe) { case PIPE_A: - temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; + /* Can only use the always-on power well for eDP when + * not using the panel fitter, and when not using motion + * blur mitigation (which we don't support). */ + if (dev_priv->pch_pf_size) + temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; + else + temp |= TRANS_DDI_EDP_INPUT_A_ON; break; case PIPE_B: temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index de3efdd..d204ed2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5607,6 +5607,35 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, return fdi_config_ok ? ret : -EINVAL; } +static void haswell_modeset_global_resources(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + bool enable = false; + struct intel_crtc *crtc; + struct intel_encoder *encoder; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { + if (crtc->pipe != PIPE_A && crtc->base.enabled) + enable = true; + /* XXX: Should check for edp transcoder here, but thanks to init + * sequence that's not yet available. Just in case desktop eDP + * on PORT D is possible on haswell, too. */ + } + + list_for_each_entry(encoder, &dev->mode_config.encoder_list, + base.head) { + if (encoder->type != INTEL_OUTPUT_EDP && + encoder->connectors_active) + enable = true; + } + + /* Even the eDP panel fitter is outside the always-on well. */ + if (dev_priv->pch_pf_size) + enable = true; + + intel_set_power_well(dev, enable); +} + static int haswell_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, @@ -8486,6 +8515,8 @@ static void intel_init_display(struct drm_device *dev) } else if (IS_HASWELL(dev)) { dev_priv->display.fdi_link_train = hsw_fdi_link_train; dev_priv->display.write_eld = haswell_write_eld; + dev_priv->display.modeset_global_resources = + haswell_modeset_global_resources; } } else if (IS_G4X(dev)) { dev_priv->display.write_eld = g4x_write_eld;