From patchwork Sat Feb 2 12:56:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 2083871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 8D9B23FD2B for ; Sat, 2 Feb 2013 13:28:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 89EA2E6315 for ; Sat, 2 Feb 2013 05:28:50 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id DA9AFE628B for ; Sat, 2 Feb 2013 05:26:17 -0800 (PST) Received: (qmail 13766 invoked by uid 0); 2 Feb 2013 13:26:17 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy3.bluehost.com with SMTP; 2 Feb 2013 13:26:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=JOOq6GRj0o5kd/qCEJivy0LUUMdc+pFdcpJvgz0g6ZM=; b=fTHFOATmfTUKPMTERYk5O4xDylx94n2NOpcDd0auFMl3FJNANr1Y6S0gWTCZomrzTdj4LgcNMRvDz2IcK9tDjbSgA23eINkzPnAdEMLdciND49H1MNoaAnAjDOvp0K84; Received: from [151.216.70.136] (port=59537 helo=jbarnes-t420.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1U1ceJ-0006Th-4d for intel-gfx@lists.freedesktop.org; Sat, 02 Feb 2013 05:56:51 -0700 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Sat, 2 Feb 2013 13:56:18 +0100 Message-Id: <1359809786-26434-15-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> References: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 151.216.70.136 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 14/22] drm/i915: add HMDI workarounds on VLV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Need to do some extra work at PLL disable time to allow HDMI to come back up on the next mode set. v2: take dpio lock around update - jbarnes only do WA on VLV -jbarnes Signed-off-by: Jesse Barnes Signed-off-by: Vijay Purushothaman --- drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2bc8ce7..c0cb254 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1492,6 +1492,14 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) int reg; u32 val; + if (IS_VALLEYVIEW(dev_priv->dev)) { + mutex_lock(&dev_priv->dpio_lock); + // Flicker WA for HDMI + intel_dpio_write(dev_priv, 0x8200, 0x00000000); + intel_dpio_write(dev_priv, 0x8204, 0x00e00060); + mutex_unlock(&dev_priv->dpio_lock); + } + /* Don't disable pipe A or pipe A PLLs if needed */ if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) return; @@ -4299,6 +4307,12 @@ static void vlv_update_pll(struct drm_crtc *crtc, * In Valleyview PLL and program lane counter registers are exposed * through DPIO interface */ + + // program DD1 Tx lane resets sets to default + // WA for HDMI flicker issue + intel_dpio_write(dev_priv, 0x8200, 0x10080); + intel_dpio_write(dev_priv, 0x8204, 0x00600060); + mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); mdiv |= ((bestn << DPIO_N_SHIFT));