From patchwork Sat Feb 2 12:56:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 2083921 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id C1F913FD2B for ; Sat, 2 Feb 2013 13:30:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B602EE62B7 for ; Sat, 2 Feb 2013 05:30:56 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy7-pub.bluehost.com (oproxy7-pub.bluehost.com [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id EA4EAE5C72 for ; Sat, 2 Feb 2013 05:26:22 -0800 (PST) Received: (qmail 28034 invoked by uid 0); 2 Feb 2013 13:26:17 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy7.bluehost.com with SMTP; 2 Feb 2013 13:26:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=LNN6k5PA2XXRkvjThTVrxDdXcPco87BYJU/Sjj9dflA=; b=NsccuXqLz8dnr2zdtDwyJfpMSaDeiB3/f3w7yEIwoHKHVZMXydL1DGDfGr1grR0+fOyMUa492SmBYY9Fr013HBT/MOrqX14BsStrrjKof5xcVfeQxxtXrxdIOB7m41gU; Received: from [151.216.70.136] (port=59537 helo=jbarnes-t420.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1U1ceN-0006Th-4C for intel-gfx@lists.freedesktop.org; Sat, 02 Feb 2013 05:56:55 -0700 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Sat, 2 Feb 2013 13:56:22 +0100 Message-Id: <1359809786-26434-19-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> References: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 151.216.70.136 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 18/22] drm/i915: add flush control reg to IS_DISPLAYREG check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org With the PTE poking code pulled into i915, we need to make sure we don't add the display offset to our TLB flush writes. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 28d5992..dde54b1 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1212,6 +1212,7 @@ static bool IS_DISPLAYREG(u32 reg) case FORCEWAKE_VLV: case FORCEWAKE_ACK_VLV: case VLV_GTLC_WAKE_CTRL: + case GFX_FLSH_CNTL_GEN6: return false; default: break;