| Message ID | 1359809786-26434-5-git-send-email-jbarnes@virtuousgeek.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Feb 02, 2013 at 01:56:08PM +0100, Jesse Barnes wrote: > We don't generally use MI_FLUSH these days, but this bit may affect > other flushing logic, so set it to be safe. > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 2bd074a..5a9e26a 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -511,6 +511,9 @@ static int init_render_ring(struct intel_ring_buffer *ring) > I915_WRITE(GFX_MODE_GEN7, > _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + if (IS_VALLEYVIEW(dev)) > + I915_WRITE(MI_MODE, I915_READ(MI_MODE) | > + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE)); Include a comment with the WA name? Also this WA seems to be present since SNB. So should the check be for 'gen>=6' instead of VLV? Hmm. It seems that used to be the case actually and then the WA was removed in commit: commit 8d79c3490aecfe6e51f0ba6f9780746fb1434954 Author: Eric Anholt <eric@anholt.net> Date: Thu Jan 19 10:50:05 2012 -0800 drm/i915: Remove the MI_FLUSH_ENABLE setting. We have always been using the wrong bit -- it's bit 12. However, the bit also doesn't do anything -- hardware has always accepted the MI_FLUSH command even when it was specced not to. Given that there is only one MI_FLUSH emitted in all of the driver stack on gen6+ (in i965_video.c of the 2d driver, and it should be using other code to do its flush instead), just remove the MI_FLUSH enable instead of trying to fix it. Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Looks like the wrong bit part was fixed at some point. This patch needs to be refreshed anyway since the code was shuffled around a bit. > } > > if (INTEL_INFO(dev)->gen >= 5) { > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2bd074a..5a9e26a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -511,6 +511,9 @@ static int init_render_ring(struct intel_ring_buffer *ring) I915_WRITE(GFX_MODE_GEN7, _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); + if (IS_VALLEYVIEW(dev)) + I915_WRITE(MI_MODE, I915_READ(MI_MODE) | + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE)); } if (INTEL_INFO(dev)->gen >= 5) {
We don't generally use MI_FLUSH these days, but this bit may affect other flushing logic, so set it to be safe. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 1 file changed, 3 insertions(+)