From patchwork Mon Feb 4 15:27:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 2092711 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id B94A63FC23 for ; Mon, 4 Feb 2013 15:36:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA240E5F02 for ; Mon, 4 Feb 2013 07:36:52 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id B5E8BE60D0 for ; Mon, 4 Feb 2013 07:29:08 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 04 Feb 2013 07:27:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,600,1355126400"; d="scan'208";a="257441627" Received: from unknown (HELO dyon.amr.corp.intel.com) ([10.255.12.132]) by orsmga001.jf.intel.com with ESMTP; 04 Feb 2013 07:29:05 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Feb 2013 15:27:09 +0000 Message-Id: <1359991705-5254-15-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> References: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> Subject: [Intel-gfx] [PATCH 14/90] assembler: Rename branch_2_offset to break_cont X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Once again, import the equivalent struct from mesa. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 16 +++++++++++++--- assembler/main.c | 8 ++++---- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h index 7b0b0da..2815256 100644 --- a/assembler/brw_structs.h +++ b/assembler/brw_structs.h @@ -1324,11 +1324,21 @@ struct brw_instruction GLuint pad1:2; /* reserved */ } da3src; + /* This is also used for gen7 IF/ELSE instructions */ struct { - GLint JIP:16; /* Gen7 bspec: both the JIP and UIP are signed 16-bit numbers */ - GLint UIP:16; - } branch_2_offset; /* for Gen6, Gen7 2-offsets branch; for Gen7 1-offset branch */ + /* Signed jump distance to the ip to jump to if all channels + * are disabled after the break or continue. It should point + * to the end of the innermost control flow block, as that's + * where some channel could get re-enabled. + */ + int jip:16; + + /* Signed jump distance to the location to resume execution + * of this channel if it's enabled for the break or continue. + */ + int uip:16; + } break_cont; GLint JIP; /* used by Gen6 CALL instructions; Gen7 JMPI */ diff --git a/assembler/main.c b/assembler/main.c index ae271b4..1b411c7 100644 --- a/assembler/main.c +++ b/assembler/main.c @@ -424,8 +424,8 @@ int main(int argc, char **argv) if (inst->second_reloc_offset) { // this is a branch instruction with two offset arguments - entry->instruction.bits3.branch_2_offset.JIP = jump_distance(inst->first_reloc_offset); - entry->instruction.bits3.branch_2_offset.UIP = jump_distance(inst->second_reloc_offset); + entry->instruction.bits3.break_cont.jip = jump_distance(inst->first_reloc_offset); + entry->instruction.bits3.break_cont.uip = jump_distance(inst->second_reloc_offset); } else if (inst->first_reloc_offset) { // this is a branch instruction with one offset argument int offset = inst->first_reloc_offset; @@ -441,7 +441,7 @@ int main(int argc, char **argv) if(!IS_GENp(6)) { entry->instruction.bits3.JIP = offset; if(entry->instruction.header.opcode == BRW_OPCODE_ELSE) - entry->instruction.bits3.branch_2_offset.UIP = 1; /* Set the istack pop count, which must always be 1. */ + entry->instruction.bits3.break_cont.uip = 1; /* Set the istack pop count, which must always be 1. */ } else if(IS_GENx(6)) { /* TODO: endif JIP pos is not in Gen6 spec. may be bits1 */ int opcode = entry->instruction.header.opcode; @@ -457,7 +457,7 @@ int main(int argc, char **argv) if(opcode == BRW_OPCODE_JMPI) entry->instruction.bits3.JIP = offset; else - entry->instruction.bits3.branch_2_offset.JIP = offset; + entry->instruction.bits3.break_cont.jip = offset; } } }