From patchwork Sat Feb 9 20:03:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2120971 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 9FECC3FCA4 for ; Sat, 9 Feb 2013 20:14:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 81E6CE5C76 for ; Sat, 9 Feb 2013 12:14:42 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f53.google.com (mail-ee0-f53.google.com [74.125.83.53]) by gabe.freedesktop.org (Postfix) with ESMTP id 154C7E5C2B for ; Sat, 9 Feb 2013 12:14:32 -0800 (PST) Received: by mail-ee0-f53.google.com with SMTP id e53so2497243eek.12 for ; Sat, 09 Feb 2013 12:14:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=TS1LpUKZN+bA963sewsnePQOXUUgNQMHVTTn6NZZgs8=; b=O6CCDQJjUTx8KPC8tUwIFn/p0yDKnYMhfvK/nkwy5ZP56j5IonoZeAl9dc228jtaoO PQ+IR7IvCEvaTDvUmrWLNB461Y/dzt6aSi+LHKHSeUzPfMg1h066EHEetvWYyjySLzZ9 3rWJNHfaHA3Ns/vzMgAPVrNpwuvK2zVJNuCMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=TS1LpUKZN+bA963sewsnePQOXUUgNQMHVTTn6NZZgs8=; b=NBZoS1S/PDI3VR0U4TnLzYZVuz6vTwSANjuLurWGDIrPjAQ7i0dumpKnqLLBMfopwx PvUCMHa80khr0cvDWqEc4eCswafMtbyJVM7sL9JKMJ4KHZVYtX67+m/lu5sbPBTCz2Wv 2r/x1bIVPqqpKQNPXvYGE1GnQlv3Z6Is7thgD7T2SkoBc7AynYaYmv48IDsTgxPRFGdz 6Y6J4GKVgpB229U5GJWR87qSoWHZw/Bz9DMn29c/9VupOy41rd18VYbWbFJxjvxZiDO/ MlLqT4KvZwPJXYP0j4XYP+ASCaXqa4PeYFrRTxTHxTuhDUw89pFSY7VE6ap3Z7GDztHf I31w== X-Received: by 10.14.4.69 with SMTP id 45mr31333417eei.0.1360440871666; Sat, 09 Feb 2013 12:14:31 -0800 (PST) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id k7sm51347738een.8.2013.02.09.12.14.29 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sat, 09 Feb 2013 12:14:30 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Sat, 9 Feb 2013 21:03:42 +0100 Message-Id: <1360440222-21830-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <20130207180907.GA723@lundgren.nims.intel.com> References: <20130207180907.GA723@lundgren.nims.intel.com> X-Gm-Message-State: ALoCoQmrNef993z34N7GFKcda+MKicb3S9EgYCkJTfARJ0RC0In1Rarm29obkDK2PnfgQDN2pYCn Cc: Daniel Vetter , Ben Widawsky , "Runyan, Arthur J" Subject: [Intel-gfx] [PATCH] drm/i915: detect wrong MCH watermark values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Some early bios versions seem to ship with the wrong tuning values for the MCH, possible resulting in pipe underruns under load. Especially on DP outputs this can lead to black screen, since DP really doesn't like an occasional whack from an underrun. Unfortunately the registers seem to be locked after boot, so the only thing we can do is politely point out issues and suggest a BIOS upgrade. Arthur Runyan pointed us at this issue while discussion DP bugs - thus far no confirmation from a bug report yet that it helps. But at least some of my machines here have wrong values, so this might be useful in understanding bug reports. v2: After a bit more discussion with Art and Ben we've decided to only the check the watermark values, since the OREF ones could be be a notch more aggressive on certain machines. Cc: Ben Widawsky Cc: Runyan, Arthur J Signed-off-by: Daniel Vetter Reviewed-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8754f91..961e2da 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1235,6 +1235,10 @@ #define MAD_DIMM_A_SIZE_SHIFT 0 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) +/** snb MCH registers for priority tuning */ +#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) +#define MCH_SSKPD_WM0_MASK 0x3f +#define MCH_SSKPD_WM0_VAL 0xc /* Clocking configuration register */ #define CLKCFG 0x10c00 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7c9a6d1..3bcc745 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3584,6 +3584,19 @@ static void cpt_init_clock_gating(struct drm_device *dev) } } +static void gen6_check_mch_setup(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t tmp; + + tmp = I915_READ(MCH_SSKPD); + if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { + DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); + DRM_INFO("This can cause pipe underruns and display issues.\n"); + DRM_INFO("Please upgrade your BIOS to fix this.\n"); + } +} + static void gen6_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -3676,6 +3689,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); cpt_init_clock_gating(dev); + + gen6_check_mch_setup(dev); } static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) @@ -3861,6 +3876,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); cpt_init_clock_gating(dev); + + gen6_check_mch_setup(dev); } static void valleyview_init_clock_gating(struct drm_device *dev)