From patchwork Wed Feb 13 11:32:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2135521 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id A8456DFE75 for ; Wed, 13 Feb 2013 11:53:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C9BA1E6643 for ; Wed, 13 Feb 2013 03:53:03 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f170.google.com (mail-we0-f170.google.com [74.125.82.170]) by gabe.freedesktop.org (Postfix) with ESMTP id 06A0BE65FC for ; Wed, 13 Feb 2013 03:43:38 -0800 (PST) Received: by mail-we0-f170.google.com with SMTP id z53so907905wey.15 for ; Wed, 13 Feb 2013 03:43:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=77peMvSebKXETrgy0oWqAkGSNs7xNWnd/Pjun+II5Ss=; b=V1bhop/Ot31bknDfdjJ9weCWEJKE/SOpcM8/pfF9WKkAFaTvNseAIg+U7BJaX+3AVE o+CU3ut3rwzNe1IA8y7n9NnsKbZvAjb7hzHAC4ER49LuweSMuSP75eMbLll+p5D2/zp4 1zyK+lt/anUCbgf/GeO9X2zk6RrWFEvA03qNM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=77peMvSebKXETrgy0oWqAkGSNs7xNWnd/Pjun+II5Ss=; b=aK5mli0JvRkpMtf3J+2+tXBm8UVgmxOqf4oAn883WjFNSoB+f/XuJn493O0YLoiwCd i9xI6z4NZsXDTIL29KSRmzdiBQjZY6jvh2OnCErc64fMCUkrUcO15OmiU73rKo2zudPG FDx5Wv/CxCpGJTNdgQxfN3dm1lYifhcXe+5gfWVGJwaNGA2Ks1OXsHg84V8gnTY6ZcXU Hhy63NF1RmaHOrN4rwhW/0mL8GYnK6jahTvbW33f0M3yJF33Yn+6ygaecNKSW8D4fQ7C zMuxh6NJmhhSZR6TLhqAcEyX8k8sgbrWPiMnQSNlCzxGbZ3nxIxIoWbS3OWRSf6Y5GQg TDJA== X-Received: by 10.180.97.197 with SMTP id ec5mr9327087wib.1.1360755817786; Wed, 13 Feb 2013 03:43:37 -0800 (PST) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id du2sm17597131wib.0.2013.02.13.03.43.36 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 13 Feb 2013 03:43:36 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 13 Feb 2013 12:32:13 +0100 Message-Id: <1360755142-19145-11-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1360755142-19145-1-git-send-email-daniel.vetter@ffwll.ch> References: <1360755142-19145-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQnj/GInJVm0ZIuG7N6SdsDFbbMDOtu6Kk6dRdZh5gZT+1jhkhleGj6LM8SF4o8o2XB5cHGo Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 10/19] drm/i915: move dp_m_n computation to dp_encoder->compute_config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We need a flag to designate dp encoders and the dp link m_n parameters in the pipe config for that. And now that the pipe bpp computations have been moved up and stored in the pipe config, too, we can do this without losing our sanity. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++----------- drivers/gpu/drm/i915/intel_dp.c | 49 +++++++----------------------------- drivers/gpu/drm/i915/intel_drv.h | 3 --- 3 files changed, 25 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ed88a6e..4ad4576 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4091,6 +4091,14 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc, } } +static void intel_dp_set_m_n(struct intel_crtc *crtc) +{ + if (crtc->config.has_pch_encoder) + intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); + else + intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); +} + static void vlv_update_pll(struct drm_crtc *crtc, intel_clock_t *clock, intel_clock_t *reduced_clock, int num_connectors) @@ -4098,9 +4106,6 @@ static void vlv_update_pll(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_display_mode *adjusted_mode = - &intel_crtc->config.adjusted_mode; - struct drm_display_mode *mode = &intel_crtc->config.requested_mode; int pipe = intel_crtc->pipe; u32 dpll, mdiv, pdiv; u32 bestn, bestm1, bestm2, bestp1, bestp2; @@ -4156,8 +4161,8 @@ static void vlv_update_pll(struct drm_crtc *crtc, intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) - intel_dp_set_m_n(crtc, mode, adjusted_mode); + if (intel_crtc->config.has_dp_encoder) + intel_dp_set_m_n(intel_crtc); I915_WRITE(DPLL(pipe), dpll); @@ -4203,9 +4208,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_display_mode *adjusted_mode = - &intel_crtc->config.adjusted_mode; - struct drm_display_mode *mode = &intel_crtc->config.requested_mode; struct intel_encoder *encoder; int pipe = intel_crtc->pipe; u32 dpll; @@ -4280,8 +4282,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc, if (encoder->pre_pll_enable) encoder->pre_pll_enable(encoder); - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) - intel_dp_set_m_n(crtc, mode, adjusted_mode); + if (intel_crtc->config.has_dp_encoder) + intel_dp_set_m_n(intel_crtc); I915_WRITE(DPLL(pipe), dpll); @@ -5435,8 +5437,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, } else intel_put_pch_pll(intel_crtc); - if (is_dp) - intel_dp_set_m_n(crtc, mode, adjusted_mode); + if (intel_crtc->config.has_dp_encoder) + intel_dp_set_m_n(intel_crtc); for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->pre_pll_enable) @@ -5580,8 +5582,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); drm_mode_debug_printmodeline(mode); - if (is_dp) - intel_dp_set_m_n(crtc, mode, adjusted_mode); + if (intel_crtc->config.has_dp_encoder) + intel_dp_set_m_n(intel_crtc); intel_crtc->lowfreq_avail = false; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0ccaeb3..37b2bd1 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -193,6 +193,8 @@ intel_dp_mode_valid(struct drm_connector *connector, if (mode->vdisplay > fixed_mode->vdisplay) return MODE_PANEL; + + target_clock = fixed_mode->clock; } max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); @@ -730,6 +732,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, if (HAS_PCH_SPLIT(dev) && !IS_HASWELL(dev) && !is_cpu_edp(intel_dp)) pipe_config->has_pch_encoder = true; + pipe_config->has_dp_encoder = true; + if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { intel_fixed_panel_mode(intel_connector->panel.fixed_mode, adjusted_mode); @@ -749,7 +753,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, /* Walk through all bpp values. Luckily they're all nicely space with 2 * bpc in between. */ - bpp = 8*3; + bpp = min_t(int, 8*3, pipe_config->pipe_bpp); if (is_edp(intel_dp)) bpp = min_t(int, bpp, dev_priv->edp.bpp); @@ -798,46 +802,11 @@ found: DRM_DEBUG_KMS("DP link bw required %i available %i\n", mode_rate, link_avail); - return true; -} - -void -intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct drm_device *dev = crtc->dev; - struct intel_encoder *intel_encoder; - struct intel_dp *intel_dp; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - int lane_count = 4; - struct intel_link_m_n m_n; + intel_link_compute_m_n(bpp, lane_count, + target_clock, adjusted_mode->clock, + &pipe_config->dp_m_n); - /* - * Find the lane count in the intel_encoder private - */ - for_each_encoder_on_crtc(dev, crtc, intel_encoder) { - intel_dp = enc_to_intel_dp(&intel_encoder->base); - - if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || - intel_encoder->type == INTEL_OUTPUT_EDP) - { - lane_count = intel_dp->lane_count; - break; - } - } - - /* - * Compute the GMCH and Link ratios. The '3' here is - * the number of bytes_per_pixel post-LUT, which we always - * set up for 8-bits of R/G/B, or 3 bytes total. - */ - intel_link_compute_m_n(intel_crtc->bpp, lane_count, - mode->clock, adjusted_mode->clock, &m_n); - - if (intel_crtc->config.has_pch_encoder) - intel_pch_transcoder_set_m_n(intel_crtc, &m_n); - else - intel_cpu_transcoder_set_m_n(intel_crtc, &m_n); + return true; } void intel_dp_init_link_config(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 341d117..8c90a64 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -458,9 +458,6 @@ extern void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, struct intel_connector *intel_connector); -void -intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode); extern void intel_dp_init_link_config(struct intel_dp *intel_dp); extern void intel_dp_start_link_train(struct intel_dp *intel_dp); extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);