| Message ID | 1360871631-20578-1-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The bit controlling whether PIPE_CONTROL DW/QW write targets > the global GTT or PPGTT moved moved from DW 2 bit 2 to > DW 1 bit 24 on IVB. > > I verified on IVB that the fix is in fact effective. Without the fix > none of the scratch writes actually landed in the pipe control page. > With the fix the writes show up correctly. > > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> [snip]
On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote: > On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > The bit controlling whether PIPE_CONTROL DW/QW write targets > > the global GTT or PPGTT moved moved from DW 2 bit 2 to > > DW 1 bit 24 on IVB. > > > > I verified on IVB that the fix is in fact effective. Without the fix > > none of the scratch writes actually landed in the pipe control page. > > With the fix the writes show up correctly. > > > > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Queued for -next, thanks for the patch. -Daniel
On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote: > On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > The bit controlling whether PIPE_CONTROL DW/QW write targets > > the global GTT or PPGTT moved moved from DW 2 bit 2 to > > DW 1 bit 24 on IVB. > > > > I verified on IVB that the fix is in fact effective. Without the fix > > none of the scratch writes actually landed in the pipe control page. > > With the fix the writes show up correctly. > > > > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Reviewed-by: Ben Widawsky <ben@bwidawsk.net> > [snip] Reading the bspec again... do we want to set bit 21?
On Tue, Feb 19, 2013 at 03:59:16PM -0800, Ben Widawsky wrote: > On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote: > > On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > The bit controlling whether PIPE_CONTROL DW/QW write targets > > > the global GTT or PPGTT moved moved from DW 2 bit 2 to > > > DW 1 bit 24 on IVB. > > > > > > I verified on IVB that the fix is in fact effective. Without the fix > > > none of the scratch writes actually landed in the pipe control page. > > > With the fix the writes show up correctly. > > > > > > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Reviewed-by: Ben Widawsky <ben@bwidawsk.net> > > [snip] > > Reading the bspec again... do we want to set bit 21? I don't think we want to do that. The scratch address we're using here is a proper GTT address, not an index into the HWS page. I have no idea why we're not using the HSW page here as well. I couldn't dig out any reason from the commit logs either. Anyone?
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d7542cd..69a95c6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -308,6 +308,7 @@ #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) +#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ #define PIPE_CONTROL_CS_STALL (1<<20) #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) #define PIPE_CONTROL_QW_WRITE (1<<14) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9b8b058..1d5d613 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -318,6 +318,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, * TLB invalidate requires a post-sync write. */ flags |= PIPE_CONTROL_QW_WRITE; + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; /* Workaround: we must issue a pipe_control with CS-stall bit * set before a pipe_control command that has the state cache @@ -331,7 +332,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); intel_ring_emit(ring, flags); - intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); + intel_ring_emit(ring, scratch_addr); intel_ring_emit(ring, 0); intel_ring_advance(ring);