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[11/13] drm/i915: add clock_get for ironlake+

Message ID 1361309508-4901-12-git-send-email-jbarnes@virtuousgeek.org (mailing list archive)
State New, archived
Headers show

Commit Message

Jesse Barnes Feb. 19, 2013, 9:31 p.m. UTC
Turns out it's easy to get the clock, though it may correspond to a
potential pfit mode.  In that case, we may still be able to flip if
we can get the native mode params somehow.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

Comments

Imre Deak March 20, 2013, 12:48 p.m. UTC | #1
On Tue, 2013-02-19 at 13:31 -0800, Jesse Barnes wrote:
> Turns out it's easy to get the clock, though it may correspond to a
> potential pfit mode.  In that case, we may still be able to flip if
> we can get the native mode params somehow.

This should be merged to 6/13.

> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   26 +++++++++++++++++++++++---
>  1 file changed, 23 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 91660b1..861af1a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6771,6 +6771,27 @@ static bool i9xx_crtc_get_mode(struct drm_crtc *crtc,
>  	return true;
>  }
>  
> +static int ironlake_crtc_clock_get(struct drm_crtc *crtc)
> +{
> +	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> +	int clock;
> +	u32 link_m;
> +
> +	/*
> +	 * PCH platforms make this easy: we can just use the LINK_M1 reg.
> +	 * Note: this may be the pixel clock for a fitted mode, in which
> +	 * case it won't match the native mode clock.  That means we won't be
> +	 * able to do a simple flip in the fastboot case.
> +	 */
> +	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
> +
> +	clock = link_m;
> +
> +	return clock;
> +}

Could be simply return I915_READ(PIPE_LINK_M1(cpu_transcoder));

> +
>  static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
>  				   struct drm_display_mode *mode)
>  {
> @@ -6797,12 +6818,11 @@ static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
>  	mode->vsync_start = (tmp & 0xffff) + 1;
>  	mode->vsync_end = ((tmp & 0xffff0000) >> 16) + 1;
>  
> -	//mode->clock = i9xx_crtc_clock_get(crtc);
> -	//mode->clock = 69300;
> +	mode->clock = ironlake_crtc_clock_get(crtc);
>  
>  	drm_mode_set_name(mode);
>  
> -	return false; /* XXX mode->clock unset */
> +	return true;
>  }
>  
>  static __maybe_unused bool no_crtc_get_mode(struct drm_crtc *crtc,
Jesse Barnes March 26, 2013, 11:29 p.m. UTC | #2
On Wed, 20 Mar 2013 14:48:22 +0200
Imre Deak <imre.deak@intel.com> wrote:

> On Tue, 2013-02-19 at 13:31 -0800, Jesse Barnes wrote:
> > Turns out it's easy to get the clock, though it may correspond to a
> > potential pfit mode.  In that case, we may still be able to flip if
> > we can get the native mode params somehow.
> 
> This should be merged to 6/13.

Done, thanks.
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 91660b1..861af1a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6771,6 +6771,27 @@  static bool i9xx_crtc_get_mode(struct drm_crtc *crtc,
 	return true;
 }
 
+static int ironlake_crtc_clock_get(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
+	int clock;
+	u32 link_m;
+
+	/*
+	 * PCH platforms make this easy: we can just use the LINK_M1 reg.
+	 * Note: this may be the pixel clock for a fitted mode, in which
+	 * case it won't match the native mode clock.  That means we won't be
+	 * able to do a simple flip in the fastboot case.
+	 */
+	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
+
+	clock = link_m;
+
+	return clock;
+}
+
 static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
 				   struct drm_display_mode *mode)
 {
@@ -6797,12 +6818,11 @@  static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
 	mode->vsync_start = (tmp & 0xffff) + 1;
 	mode->vsync_end = ((tmp & 0xffff0000) >> 16) + 1;
 
-	//mode->clock = i9xx_crtc_clock_get(crtc);
-	//mode->clock = 69300;
+	mode->clock = ironlake_crtc_clock_get(crtc);
 
 	drm_mode_set_name(mode);
 
-	return false; /* XXX mode->clock unset */
+	return true;
 }
 
 static __maybe_unused bool no_crtc_get_mode(struct drm_crtc *crtc,