From patchwork Thu Feb 21 00:50:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2169941 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 1595D3FD4E for ; Thu, 21 Feb 2013 00:57:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA3F5E68A5 for ; Wed, 20 Feb 2013 16:57:25 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f174.google.com (mail-ea0-f174.google.com [209.85.215.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E4A2E5FE4 for ; Wed, 20 Feb 2013 16:50:58 -0800 (PST) Received: by mail-ea0-f174.google.com with SMTP id 1so3641748eaa.5 for ; Wed, 20 Feb 2013 16:50:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=pBCgpv+vVDM5clJS/HE+kyd0uyl1/PsJBoQOTVFJQJQ=; b=Qr186yROJ8YopdsJWzXpGAbVdHNYaW8/BHViiybvXmfutKjKz0a6phqeGdPs0o6lRA IXVkkzAP8AlyqL2CPGh536A4F6Zk7uirLAI7Y1kZmwTY4oANIU5dADMI4nQSdH+ma2HP QQqFwCADklPnQFGpPjvFYitKg39bjIra9VouM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=pBCgpv+vVDM5clJS/HE+kyd0uyl1/PsJBoQOTVFJQJQ=; b=GgY7nuIu3nNiUyP2rgzWLgziuzbCruWwoE4wiF2B4qU2aKbS0gJIvUKDACmK9bSaGY u1TRpZKO7ydCS5nRCQQ+DV9o1YZgNYcmEFd+mN7ZINXDdqqhnUN9We4ZmOtIYl3G5ZCV qWqc1QxCm88kCnCkPWNektxZrmbmf5oA/AvgS6wJjwcLwT1LhUx+sgOMEoadZ/Br/ytw 0ymdUPd1DYcUj4wNv33ypMCegAeN9HvI5Eoe34Cc8F64eGA3l8hrVkHhbSkV9+MMtOUl Yn5tuaKjZFE/9PMJX2SnYZg4RUpMHGI80wZP/hlJtZtjw6K56zmONBotetIOq/A7Eb6/ CQiw== X-Received: by 10.14.3.133 with SMTP id 5mr74040965eeh.43.1361407857461; Wed, 20 Feb 2013 16:50:57 -0800 (PST) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id d47sm53318783eem.9.2013.02.20.16.50.55 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 20 Feb 2013 16:50:56 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 21 Feb 2013 01:50:03 +0100 Message-Id: <1361407828-2419-12-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1361407828-2419-1-git-send-email-daniel.vetter@ffwll.ch> References: <1361407828-2419-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmjjDVmUBmcU5eGBH1yG04LKZ56VRsimd8wqAMDATIx6J9kliO4+/EHmyFsFiJOYpQvS0L1 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 11/36] drm/i915: track dp target_clock in pipe_config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We need it in the fdi m_n computation, which nicely kills almost all ugly special cases in there. It looks like we also need this to handle 12bpc hdmi correctly. Eventually it might be better to switch things around and put the target clock into adjusted_mode->clock and create a new pipe_config parameter for the port link clock. v2: Add a massive comment in the code to explain this mess. v3: s/dp_target_clock/pixel_target_clock in anticipation of the hdmi use-case. Signed-off-by: Daniel Vetter maybe-fixup: Make pipe_config->dp_target_clock more useful --- drivers/gpu/drm/i915/intel_display.c | 25 +++---------------------- drivers/gpu/drm/i915/intel_dp.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 6 ++++++ 3 files changed, 10 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 655f78fb..3f0b9f8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5203,25 +5203,9 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_display_mode *adjusted_mode = &intel_crtc->config.adjusted_mode; - struct drm_display_mode *mode = &intel_crtc->config.requested_mode; - struct intel_encoder *intel_encoder, *edp_encoder = NULL; struct intel_link_m_n m_n = {0}; int target_clock, lane, link_bw; - bool is_dp = false, is_cpu_edp = false; - - for_each_encoder_on_crtc(dev, crtc, intel_encoder) { - switch (intel_encoder->type) { - case INTEL_OUTPUT_DISPLAYPORT: - is_dp = true; - break; - case INTEL_OUTPUT_EDP: - is_dp = true; - if (!intel_encoder_is_pch_edp(&intel_encoder->base)) - is_cpu_edp = true; - edp_encoder = intel_encoder; - break; - } - } + uint32_t bps; /* FDI is a binary signal running at ~2.7GHz, encoding * each output octet as 10 bits. The actual frequency @@ -5232,11 +5216,8 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) */ link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; - /* [e]DP over FDI requires target mode clock instead of link clock. */ - if (edp_encoder) - target_clock = intel_edp_target_clock(edp_encoder, mode); - else if (is_dp) - target_clock = mode->clock; + if (intel_crtc->config.pixel_target_clock) + target_clock = intel_crtc->config.pixel_target_clock; else target_clock = adjusted_mode->clock; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2b12f1c..59e3348 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -795,6 +795,7 @@ found: intel_dp->lane_count = lane_count; adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); pipe_config->pipe_bpp = bpp; + pipe_config->pixel_target_clock = target_clock; DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", intel_dp->link_bw, intel_dp->lane_count, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 69ec74c..64c167c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -192,6 +192,12 @@ struct intel_crtc_config { bool dither; int pipe_bpp; struct intel_link_m_n dp_m_n; + /** + * This is currently used by DP and HDMI encoders since those can have a + * target pixel clock != the port link clock (which is currently stored + * in adjusted_mode->clock). + */ + int pixel_target_clock; /* Used by SDVO (and if we ever fix it, HDMI). */ unsigned pixel_multiplier; };