From patchwork Thu Feb 21 00:50:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2170101 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 2E6F4DF230 for ; Thu, 21 Feb 2013 01:05:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3106E685D for ; Wed, 20 Feb 2013 17:05:23 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f47.google.com (mail-ee0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTP id 7606FE6890 for ; Wed, 20 Feb 2013 16:51:27 -0800 (PST) Received: by mail-ee0-f47.google.com with SMTP id e52so4208064eek.6 for ; Wed, 20 Feb 2013 16:51:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=yO0X2G2tObLS/gQjPuielcEF64OCoyxfgv299qnIxeo=; b=aHX2Z2EgIGsBHu3g7jP55WHsWc/irvOh8b3ukwJCU4szplfNBNGDNLiofVnf/RJC+I x3fq4dEbBZOcWGKRBJG3jYRKMGwBb8AjDwQpz8Tb4/WcRzKxxSiLkDMcsmq1nZnrMohT H0jGdFrF8zyfkMJKjJreNiHaOgMLmltytXsi4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=yO0X2G2tObLS/gQjPuielcEF64OCoyxfgv299qnIxeo=; b=U7gCae9TthN4NieYUYAJlUhoAoUqjzcMOr+SQ6HG+g7BlGsuNsXWmm1nMbwoPgjr1m eiibGcvNQy1GPgZAJyg6ERHvr3gQ2GnWbe2qtqXBmVIO6AeEpVDNezq8oaZlWHAGybD/ AskLzrlLCXcwM9qxkvzSKcaoWYGKYkum0vdvQJeboKw4vHgLvnl9sbJYhlNpza/PNuwe tsarl8oGSBO1xT8vwKEWrn4En4eH0OQhHr5OEVV5dHXcfxFfMZuj2SacxkxN/Rp+9czi LLO0Nf2aHWXtUEUAuTK/xb8f+p1K+WlNBHANq6g5Cc+dqpP1980g7pvj0A6fxqIc2/BY hkKg== X-Received: by 10.14.223.69 with SMTP id u45mr74538907eep.23.1361407886656; Wed, 20 Feb 2013 16:51:26 -0800 (PST) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id d47sm53318783eem.9.2013.02.20.16.51.24 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 20 Feb 2013 16:51:25 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 21 Feb 2013 01:50:19 +0100 Message-Id: <1361407828-2419-28-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1361407828-2419-1-git-send-email-daniel.vetter@ffwll.ch> References: <1361407828-2419-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmhqqlWqF2HHPcBgfaGvLyTHqh+dgBVL2yYfc8D6x8Ys8siks+YGY4AWClmTkGxH6W9BDcb Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 27/36] drm/i915: extract i9xx_set_pipeconf X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Prep-patch to improve the bpc handling in a next patch. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 120 +++++++++++++++++++---------------- 1 file changed, 65 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0dc06bb..37c9a9e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4319,6 +4319,68 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); } +static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) +{ + struct drm_device *dev = intel_crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t pipeconf; + + pipeconf = I915_READ(PIPECONF(intel_crtc->pipe)); + + if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { + /* Enable pixel doubling when the dot clock is > 90% of the (display) + * core speed. + * + * XXX: No double-wide on 915GM pipe B. Is that the only reason for the + * pipe == 0 check? + */ + if (intel_crtc->config.requested_mode.clock > + dev_priv->display.get_display_clock_speed(dev) * 9 / 10) + pipeconf |= PIPECONF_DOUBLE_WIDE; + else + pipeconf &= ~PIPECONF_DOUBLE_WIDE; + } + + /* default to 8bpc */ + pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); + if (intel_crtc->config.has_dp_encoder) { + if (intel_crtc->config.dither) { + pipeconf |= PIPECONF_6BPC | + PIPECONF_DITHER_EN | + PIPECONF_DITHER_TYPE_SP; + } + } + + if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base, + INTEL_OUTPUT_EDP)) { + if (intel_crtc->config.dither) { + pipeconf |= PIPECONF_6BPC | + PIPECONF_ENABLE | + I965_PIPECONF_ACTIVE; + } + } + + if (HAS_PIPE_CXSR(dev)) { + if (intel_crtc->lowfreq_avail) { + DRM_DEBUG_KMS("enabling CxSR downclocking\n"); + pipeconf |= PIPECONF_CXSR_DOWNCLOCK; + } else { + DRM_DEBUG_KMS("disabling CxSR downclocking\n"); + pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; + } + } + + pipeconf &= ~PIPECONF_INTERLACE_MASK; + if (!IS_GEN2(dev) && + intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) + pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; + else + pipeconf |= PIPECONF_PROGRESSIVE; + + I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); + POSTING_READ(PIPECONF(intel_crtc->pipe)); +} + static int i9xx_crtc_mode_set(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *fb) @@ -4333,7 +4395,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, int plane = intel_crtc->plane; int refclk, num_connectors = 0; intel_clock_t clock, reduced_clock; - u32 dspcntr, pipeconf; + u32 dspcntr; bool ok, has_reduced_clock = false, is_sdvo = false; bool is_lvds = false, is_tv = false; struct intel_encoder *encoder; @@ -4413,9 +4475,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, has_reduced_clock ? &reduced_clock : NULL, num_connectors); - /* setup pipeconf */ - pipeconf = I915_READ(PIPECONF(pipe)); - /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; @@ -4424,58 +4483,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, else dspcntr |= DISPPLANE_SEL_PIPE_B; - if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { - /* Enable pixel doubling when the dot clock is > 90% of the (display) - * core speed. - * - * XXX: No double-wide on 915GM pipe B. Is that the only reason for the - * pipe == 0 check? - */ - if (mode->clock > - dev_priv->display.get_display_clock_speed(dev) * 9 / 10) - pipeconf |= PIPECONF_DOUBLE_WIDE; - else - pipeconf &= ~PIPECONF_DOUBLE_WIDE; - } - - /* default to 8bpc */ - pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); - if (intel_crtc->config.has_dp_encoder) { - if (intel_crtc->config.dither) { - pipeconf |= PIPECONF_6BPC | - PIPECONF_DITHER_EN | - PIPECONF_DITHER_TYPE_SP; - } - } - - if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { - if (intel_crtc->config.dither) { - pipeconf |= PIPECONF_6BPC | - PIPECONF_ENABLE | - I965_PIPECONF_ACTIVE; - } - } - DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); drm_mode_debug_printmodeline(mode); - if (HAS_PIPE_CXSR(dev)) { - if (intel_crtc->lowfreq_avail) { - DRM_DEBUG_KMS("enabling CxSR downclocking\n"); - pipeconf |= PIPECONF_CXSR_DOWNCLOCK; - } else { - DRM_DEBUG_KMS("disabling CxSR downclocking\n"); - pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; - } - } - - pipeconf &= ~PIPECONF_INTERLACE_MASK; - if (!IS_GEN2(dev) && - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) - pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; - else - pipeconf |= PIPECONF_PROGRESSIVE; - intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); /* pipesrc and dspsize control the size that is scaled from, @@ -4486,8 +4496,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, (mode->hdisplay - 1)); I915_WRITE(DSPPOS(plane), 0); - I915_WRITE(PIPECONF(pipe), pipeconf); - POSTING_READ(PIPECONF(pipe)); + i9xx_set_pipeconf(intel_crtc); + intel_enable_pipe(dev_priv, pipe, false); intel_wait_for_vblank(dev, pipe);