From patchwork Thu Feb 21 23:56:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2173731 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 922C9DF215 for ; Fri, 22 Feb 2013 00:00:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 657BBE6229 for ; Thu, 21 Feb 2013 16:00:55 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f182.google.com (mail-ea0-f182.google.com [209.85.215.182]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C535E620D for ; Thu, 21 Feb 2013 15:57:13 -0800 (PST) Received: by mail-ea0-f182.google.com with SMTP id a12so35176eaa.41 for ; Thu, 21 Feb 2013 15:57:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=5bIMYKhihJysBt9LxELZ0bKQL4LKSCm+c7k+vwz0m5M=; b=LkcMxMEcuGTAOb43Byy0SJwGl9RF3lMpyz4Kia2Rb3GAj7xuWpNeQn2xjvclZ9oGhw ikfrvcflT4zg0xn1sxd1IfDcECXd0kAzQZvbgJQfKzzF9VcRWcCq8qEjAKncXaKrik9j Wg1x7mQk0VseK9j3SToFtz/UHhucAjMVx1C/Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=5bIMYKhihJysBt9LxELZ0bKQL4LKSCm+c7k+vwz0m5M=; b=o5BjFkPWpU+lGevrCOSoEYlIvWk200ahXLrTD5knyb4hYM2W5uyvUby2Q7vq4/crTc EghVYpIzyd/GjICEf3rtnOUl5J22Pn6Kg9T0xGkYIF02xtXUzLNGNkL3Em1ofTHxQiz4 u1g9MCgtilKdPnn+NimY7+k3cWn3u7oTs3lJwVmGHW0P/eHAyf9V4dz8k6PwpNTMQ9NO 3eLwyEI4qMrz5NfnXJp9xAbeKQ1kha2F6O64Y4ZGCDLoVBYuATCsbfM4p5yDVytL23fJ 5yuxfwye5yxl67YloWTEpWTfW1B6MiSeO3CCv9TlozrUvl+QvW/KXY9XIMWer+SN6NDa QqnA== X-Received: by 10.14.0.135 with SMTP id 7mr14971eeb.5.1361491032587; Thu, 21 Feb 2013 15:57:12 -0800 (PST) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id q5sm456579eep.11.2013.02.21.15.57.10 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 21 Feb 2013 15:57:11 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 22 Feb 2013 00:56:51 +0100 Message-Id: <1361491014-13888-8-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1361491014-13888-1-git-send-email-daniel.vetter@ffwll.ch> References: <1361491014-13888-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQkbQ6kiFqKjHs7RpFHoDlfDpTPQAWMv4IukRyiqNY0tJsyT3TQi/0vXE41IGSElB6jVBhEd Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 07/10] drm/i915: add pipe_config->limited_color_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Now that we have a useful struct for this, let's use it. Some neat pointer-chasing required, but it's all there already. v2: Rebased on top of the added Haswell limited color range support. Signed-off-by: Daniel Vetter Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 13 ++++++------- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 12 +++++++----- drivers/gpu/drm/i915/intel_hdmi.c | 5 +++-- drivers/gpu/drm/i915/intel_sdvo.c | 5 +++-- 5 files changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c5f7c6e..a19778c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5131,7 +5131,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc, else val |= PIPECONF_PROGRESSIVE; - if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) + if (intel_crtc->config.limited_color_range) val |= PIPECONF_COLOR_RANGE_SELECT; else val &= ~PIPECONF_COLOR_RANGE_SELECT; @@ -5147,8 +5147,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc, * is supported, but eventually this should handle various * RGB<->YCbCr scenarios as well. */ -static void intel_set_pipe_csc(struct drm_crtc *crtc, - const struct drm_display_mode *adjusted_mode) +static void intel_set_pipe_csc(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -5163,7 +5162,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc, * consideration. */ - if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) + if (intel_crtc->config.limited_color_range) coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ /* @@ -5187,7 +5186,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc, if (INTEL_INFO(dev)->gen > 6) { uint16_t postoff = 0; - if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) + if (intel_crtc->config.limited_color_range) postoff = (16 * (1 << 13) / 255) & 0x1fff; I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); @@ -5198,7 +5197,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc, } else { uint32_t mode = CSC_MODE_YUV_TO_RGB; - if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) + if (intel_crtc->config.limited_color_range) mode |= CSC_BLACK_SCREEN_OFFSET; I915_WRITE(PIPE_CSC_MODE(pipe), mode); @@ -5794,7 +5793,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, haswell_set_pipeconf(crtc, adjusted_mode, dither); - intel_set_pipe_csc(crtc, adjusted_mode); + intel_set_pipe_csc(crtc); /* Set up the display plane register */ I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index e851fdd..0f15513 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -739,7 +739,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, } if (intel_dp->color_range) - adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; + pipe_config->limited_color_range = true; mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 458e6bd..61ce435 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -103,11 +103,6 @@ /* drm_display_mode->private_flags */ #define INTEL_MODE_DP_FORCE_6BPC (0x10) -/* - * Set when limited 16-235 (as opposed to full 0-255) RGB color range is - * to be used. - */ -#define INTEL_MODE_LIMITED_COLOR_RANGE (0x40) struct intel_framebuffer { struct drm_framebuffer base; @@ -192,6 +187,13 @@ struct intel_crtc_config { /* Whether to set up the PCH/FDI. Note that we never allow sharing * between pch encoders and cpu encoders. */ bool has_pch_encoder; + + /* + * Use reduced/limited/broadcast rbg range, compressing from the full + * range fed into the crtcs. + */ + bool limited_color_range; + /* Used by SDVO (and if we ever fix it, HDMI). */ unsigned pixel_multiplier; }; diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index cfc9d751..a8e7104 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -332,6 +332,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, struct drm_display_mode *adjusted_mode) { struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct dip_infoframe avi_if = { .type = DIP_TYPE_AVI, .ver = DIP_VERSION_AVI, @@ -342,7 +343,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; if (intel_hdmi->rgb_quant_range_selectable) { - if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) + if (intel_crtc->config.limited_color_range) avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; else avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; @@ -789,7 +790,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, } if (intel_hdmi->color_range) - adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; + pipe_config->limited_color_range = true; if (HAS_PCH_SPLIT(dev) && !IS_HASWELL(dev)) pipe_config->has_pch_encoder = true; diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 7100196..59a6781 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -956,9 +956,10 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, .len = DIP_LEN_AVI, }; uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)]; + struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc); if (intel_sdvo->rgb_quant_range_selectable) { - if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) + if (intel_crtc->config.limited_color_range) avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; else avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; @@ -1087,7 +1088,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, } if (intel_sdvo->color_range) - adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; + pipe_config->limited_color_range = true; return true; }