From patchwork Fri Feb 22 00:00:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2173841 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 495E1DF215 for ; Fri, 22 Feb 2013 00:07:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C792E61F1 for ; Thu, 21 Feb 2013 16:07:52 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f52.google.com (mail-ee0-f52.google.com [74.125.83.52]) by gabe.freedesktop.org (Postfix) with ESMTP id 01368E612B for ; Thu, 21 Feb 2013 16:01:09 -0800 (PST) Received: by mail-ee0-f52.google.com with SMTP id b15so40799eek.11 for ; Thu, 21 Feb 2013 16:01:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=dipLFS1ugtVHt1LLFL8CYqj52HeJak1VEhZSR6fR6J8=; b=XXCjPEYIY9QkZMl0vUd/0SOj6wNlyeBDYJ+Abib/i3j1k5q6W+ra7m3tj28k67LZDX 51oT8sOYum85mrJlp+/TXP7/bLgIHYevZzAejvLGEwRmlWxI1m7PqVkBiord3TBnLPCC SSt41qO6Ok4ZEmzF8BXK+aHEi0XrCWf7EZzKs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=dipLFS1ugtVHt1LLFL8CYqj52HeJak1VEhZSR6fR6J8=; b=h16tdqkN7LZb89FOxldCvEi5lrhWS6X0v4GR/9YxMaBbpVsy5cmmq5aIzhldr6A0nS 1DABpOldpx8qQVhazCrNzQ4CderNKN/m5mlLt6PF/QntmH+9oGVPc6G1wenNOkZ9k+MA r3yENLzIN91H9ZHMUaQLDO0umIAEpAlZg9UK6psCLUUZ8l1YGpAgf8ASFLJWd9j9NxHy 8KHc2Fq1aIFmgRlH3UAc4bMg0Do6J1VuD6Tstxf6SFGL2yhdq7ui7pUYc7bB3kvyiCZv YY+0wKZoTv3tvqs0gvSrbCfRMI3SFCRhuC1uZdYt1/z1uKOeagGdg7JDcsKLWRL23yRM 94KQ== X-Received: by 10.14.210.8 with SMTP id t8mr86161912eeo.35.1361491269228; Thu, 21 Feb 2013 16:01:09 -0800 (PST) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id 44sm491061eek.5.2013.02.21.16.01.07 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 21 Feb 2013 16:01:08 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 22 Feb 2013 01:00:48 +0100 Message-Id: <1361491248-14059-9-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1361491248-14059-1-git-send-email-daniel.vetter@ffwll.ch> References: <1361491248-14059-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmcia6njPFdCoUj7sHT2IPMkZlgkNSC/SEuEPwNoFM6TjZ452kUuxcZMxbOlLy4DtId5GWN Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 8/8] drm/i915: move dp clock computations to encoder->compute_config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org With the exception of hsw, which has dedicated DP clocks which run at the fixed frequency already, and vlv, which doesn't have optmized pre-defined dp clock parameters (yet). Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 97 +----------------------------------- drivers/gpu/drm/i915/intel_dp.c | 45 +++++++++++++++++ 2 files changed, 46 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2f9b3ce..45a52f3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -98,15 +98,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, intel_clock_t *best_clock); static bool -intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, - int target, int refclk, intel_clock_t *match_clock, - intel_clock_t *best_clock); -static bool -intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, - int target, int refclk, intel_clock_t *match_clock, - intel_clock_t *best_clock); - -static bool intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *match_clock, intel_clock_t *best_clock); @@ -238,20 +229,6 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { .find_pll = intel_g4x_find_best_PLL, }; -static const intel_limit_t intel_limits_g4x_display_port = { - .dot = { .min = 161670, .max = 227000 }, - .vco = { .min = 1750000, .max = 3500000}, - .n = { .min = 1, .max = 2 }, - .m = { .min = 97, .max = 108 }, - .m1 = { .min = 0x10, .max = 0x12 }, - .m2 = { .min = 0x05, .max = 0x06 }, - .p = { .min = 10, .max = 20 }, - .p1 = { .min = 1, .max = 2}, - .p2 = { .dot_limit = 0, - .p2_slow = 10, .p2_fast = 10 }, - .find_pll = intel_find_pll_g4x_dp, -}; - static const intel_limit_t intel_limits_pineview_sdvo = { .dot = { .min = 20000, .max = 400000}, .vco = { .min = 1700000, .max = 3500000 }, @@ -358,20 +335,6 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { .find_pll = intel_g4x_find_best_PLL, }; -static const intel_limit_t intel_limits_ironlake_display_port = { - .dot = { .min = 25000, .max = 350000 }, - .vco = { .min = 1760000, .max = 3510000}, - .n = { .min = 1, .max = 2 }, - .m = { .min = 81, .max = 90 }, - .m1 = { .min = 12, .max = 22 }, - .m2 = { .min = 5, .max = 9 }, - .p = { .min = 10, .max = 20 }, - .p1 = { .min = 1, .max = 2}, - .p2 = { .dot_limit = 0, - .p2_slow = 10, .p2_fast = 10 }, - .find_pll = intel_find_pll_ironlake_dp, -}; - static const intel_limit_t intel_limits_vlv_dac = { .dot = { .min = 25000, .max = 270000 }, .vco = { .min = 4000000, .max = 6000000 }, @@ -482,10 +445,7 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, else limit = &intel_limits_ironlake_single_lvds; } - } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || - intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) - limit = &intel_limits_ironlake_display_port; - else + } else limit = &intel_limits_ironlake_dac; return limit; @@ -508,8 +468,6 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) limit = &intel_limits_g4x_hdmi; } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { limit = &intel_limits_g4x_sdvo; - } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { - limit = &intel_limits_g4x_display_port; } else /* The option is for other outputs */ limit = &intel_limits_i9xx_sdvo; @@ -752,59 +710,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, } static bool -intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, - int target, int refclk, intel_clock_t *match_clock, - intel_clock_t *best_clock) -{ - struct drm_device *dev = crtc->dev; - intel_clock_t clock; - - if (target < 200000) { - clock.n = 1; - clock.p1 = 2; - clock.p2 = 10; - clock.m1 = 12; - clock.m2 = 9; - } else { - clock.n = 2; - clock.p1 = 1; - clock.p2 = 10; - clock.m1 = 14; - clock.m2 = 8; - } - intel_clock(dev, refclk, &clock); - memcpy(best_clock, &clock, sizeof(intel_clock_t)); - return true; -} - -/* DisplayPort has only two frequencies, 162MHz and 270MHz */ -static bool -intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, - int target, int refclk, intel_clock_t *match_clock, - intel_clock_t *best_clock) -{ - intel_clock_t clock; - if (target < 200000) { - clock.p1 = 2; - clock.p2 = 10; - clock.n = 2; - clock.m1 = 23; - clock.m2 = 8; - } else { - clock.p1 = 1; - clock.p2 = 10; - clock.n = 1; - clock.m1 = 14; - clock.m2 = 2; - } - clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); - clock.p = (clock.p1 * clock.p2); - clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; - clock.vco = 0; - memcpy(best_clock, &clock, sizeof(intel_clock_t)); - return true; -} -static bool intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *match_clock, intel_clock_t *best_clock) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3261242..83e3791 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -670,6 +670,49 @@ intel_dp_i2c_init(struct intel_dp *intel_dp, return ret; } +static void +intel_dp_set_clock(struct intel_encoder *encoder, + struct intel_crtc_config *pipe_config, int link_bw) +{ + struct drm_device *dev = encoder->base.dev; + + if (IS_G4X(dev)) { + if (link_bw == DP_LINK_BW_1_62) { + pipe_config->dpll.p1 = 2; + pipe_config->dpll.p2 = 10; + pipe_config->dpll.n = 2; + pipe_config->dpll.m1 = 23; + pipe_config->dpll.m2 = 8; + } else { + pipe_config->dpll.p1 = 1; + pipe_config->dpll.p2 = 10; + pipe_config->dpll.n = 1; + pipe_config->dpll.m1 = 14; + pipe_config->dpll.m2 = 2; + } + pipe_config->clock_set = true; + } else if (IS_HASWELL(dev)) { + /* Haswell has special-purpose DP DDI clocks. */ + } else if (HAS_PCH_SPLIT(dev)) { + if (link_bw == DP_LINK_BW_1_62) { + pipe_config->dpll.n = 1; + pipe_config->dpll.p1 = 2; + pipe_config->dpll.p2 = 10; + pipe_config->dpll.m1 = 12; + pipe_config->dpll.m2 = 9; + } else { + pipe_config->dpll.n = 2; + pipe_config->dpll.p1 = 1; + pipe_config->dpll.p2 = 10; + pipe_config->dpll.m1 = 14; + pipe_config->dpll.m2 = 8; + } + pipe_config->clock_set = true; + } else if (IS_VALLEYVIEW(dev)) { + /* FIXME: Need to figure out optimized DP clocks for vlv. */ + } +} + bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) @@ -765,6 +808,8 @@ found: target_clock, adjusted_mode->clock, &pipe_config->dp_m_n); + intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); + return true; }