From patchwork Fri Feb 22 00:05:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2173931 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id C1B48DF215 for ; Fri, 22 Feb 2013 00:12:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B3BBE6202 for ; Thu, 21 Feb 2013 16:12:48 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f169.google.com (mail-ea0-f169.google.com [209.85.215.169]) by gabe.freedesktop.org (Postfix) with ESMTP id 02E46E61A4 for ; Thu, 21 Feb 2013 16:05:42 -0800 (PST) Received: by mail-ea0-f169.google.com with SMTP id d13so38058eaa.28 for ; Thu, 21 Feb 2013 16:05:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=x6SheN3RcbityMMQlSJR9eKlwnlvm0eaLofoFetg8t8=; b=LkHgLA6tukOhaDlELCLrYxkw79Ul6WfMJwpkzxk6WzmwWnLk6iMiumZ8Uaha3IxE7I CodP4NPQ7L1tlS0UIyFcVX7Yzh2s4Iv3wdeDpEwPI1XdcgTfSSYAq1Dct9CLnUkanf1r 6EfN0HPwhj/bhfg9KxV7bmc1HGTryFQ1+3KPM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=x6SheN3RcbityMMQlSJR9eKlwnlvm0eaLofoFetg8t8=; b=YXimTKyRW+8PTEH4Trr0/ZsYs/TZMGWIoPk29fzVYFhc2kITiH+TRY5HveGahaNlAl 55ryQHDY+grKGkhIkV8l6MS3FLE4hgknR3M2kgg9WqTn4Xxw/TmBQZTDIThiPpAcDMEl 5d4gMj4ClGgga6U+SibIXaRxGNZ29x5YphItDiNjtLR2gHcYeNUfHGGw0q/pU1WndXPR kvwLFTQZAvqNOU/y7PYrt5jaXLuTFHZS8TJmWJUtjOWe1gPyRUz0KWeN1BqdqCCOACN/ hTEdabYnE7oRKyosqsTnK3/G2ckrJmBVNAKg6D/K6pjvzQ7hc+bbOFMPMd2rL3UIMQAF oFOA== X-Received: by 10.14.214.66 with SMTP id b42mr86242178eep.34.1361491542157; Thu, 21 Feb 2013 16:05:42 -0800 (PST) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id s3sm508871eem.4.2013.02.21.16.05.40 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 21 Feb 2013 16:05:41 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 22 Feb 2013 01:05:04 +0100 Message-Id: <1361491513-14231-10-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1361491513-14231-1-git-send-email-daniel.vetter@ffwll.ch> References: <1361491513-14231-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQls0XJdTxD20+PEN8Ak94Gd3lrSHAYIVi/ZVeFEIh16Ae+KZDnZubMLyid3y9LI46xivG97 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 5/8] drm/i915: add hw state readout/checking for pipe_config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We need to be able to read out the hw state code for a bunch of reasons: - Correctly disabling boot-up/resume state. - Pure paranoia. Since not all of the pipe configuration is e.g. relevant for fastboot (or at least we can allow some wiggle room in some parameters, like the clocks), we need to add a strict_checking parameter to intel_pipe_config_compare for fastboot. For now intel_pipe_config_compare should be fully paranoid and check everything that the hw state readout code supports. Which for this infrastructure code is nothing. I've gone a bit overboard with adding 3 get_pipe_config functions: The ilk version will differ with the next patch, so it's not too onerous. v2: Don't check the hw config if the pipe is off, since an enabled, but dpms off crtc will obviously have tons of difference with the hw state. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 5 +++ drivers/gpu/drm/i915/intel_display.c | 77 +++++++++++++++++++++++++++++++----- 2 files changed, 72 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8fb14fb..7484ea8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -272,6 +272,7 @@ struct drm_i915_error_state { }; struct intel_crtc_config; +struct intel_crtc; struct drm_i915_display_funcs { bool (*fbc_enabled)(struct drm_device *dev); @@ -285,6 +286,10 @@ struct drm_i915_display_funcs { void (*update_linetime_wm)(struct drm_device *dev, int pipe, struct drm_display_mode *mode); void (*modeset_global_resources)(struct drm_device *dev); + /* Returns the active state of the crtc, and if the crtc is active, + * fills out the pipe-config with the hw state. */ + bool (*get_pipe_config)(struct intel_crtc *, + struct intel_crtc_config *); int (*crtc_mode_set)(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d4efe97..ba9adf7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4636,6 +4636,20 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, return ret; } +static bool i9xx_get_pipe_config(struct intel_crtc *crtc, + struct intel_crtc_config *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t tmp; + + tmp = I915_READ(PIPECONF(crtc->pipe)); + if (!(tmp & PIPECONF_ENABLE)) + return false; + + return true; +} + static void ironlake_init_pch_refclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -5296,7 +5310,6 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) &intel_crtc->config.adjusted_mode; struct intel_link_m_n m_n = {0}; int target_clock, lane, link_bw; - uint32_t bps; /* FDI is a binary signal running at ~2.7GHz, encoding * each output octet as 10 bits. The actual frequency @@ -5552,6 +5565,20 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, return fdi_config_ok ? ret : -EINVAL; } +static bool ironlake_get_pipe_config(struct intel_crtc *crtc, + struct intel_crtc_config *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t tmp; + + tmp = I915_READ(PIPECONF(crtc->pipe)); + if (!(tmp & PIPECONF_ENABLE)) + return false; + + return true; +} + static void haswell_modeset_global_resources(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -5661,6 +5688,20 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, return ret; } +static bool haswell_get_pipe_config(struct intel_crtc *crtc, + struct intel_crtc_config *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t tmp; + + tmp = I915_READ(PIPECONF(crtc->cpu_transcoder)); + if (!(tmp & PIPECONF_ENABLE)) + return false; + + return true; +} + static int intel_crtc_mode_set(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *fb) @@ -7596,12 +7637,21 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) base.head) \ if (mask & (1 <<(intel_crtc)->pipe)) \ +static bool +intel_pipe_config_compare(struct intel_crtc_config *current_config, + struct intel_crtc_config *pipe_config) +{ + return true; +} + void intel_modeset_check_state(struct drm_device *dev) { + drm_i915_private_t *dev_priv = dev->dev_private; struct intel_crtc *crtc; struct intel_encoder *encoder; struct intel_connector *connector; + struct intel_crtc_config pipe_config; list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { @@ -7690,7 +7740,15 @@ intel_modeset_check_state(struct drm_device *dev) "crtc's computed enabled state doesn't match tracked enabled state " "(expected %i, found %i)\n", enabled, crtc->base.enabled); - assert_pipe(dev->dev_private, crtc->pipe, crtc->active); + active = dev_priv->display.get_pipe_config(crtc, + &pipe_config); + WARN(crtc->active != active, + "crtc active state doesn't match with hw state " + "(expected %i, found %i)\n", crtc->active, active); + + WARN(active && + !intel_pipe_config_compare(&crtc->config, &pipe_config), + "pipe state doesn't match!\n"); } } @@ -8502,18 +8560,21 @@ static void intel_init_display(struct drm_device *dev) /* We always want a DPMS function */ if (HAS_DDI(dev)) { + dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; dev_priv->display.crtc_enable = haswell_crtc_enable; dev_priv->display.crtc_disable = haswell_crtc_disable; dev_priv->display.off = haswell_crtc_off; dev_priv->display.update_plane = ironlake_update_plane; } else if (HAS_PCH_SPLIT(dev)) { + dev_priv->display.get_pipe_config = ironlake_get_pipe_config; dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; dev_priv->display.crtc_enable = ironlake_crtc_enable; dev_priv->display.crtc_disable = ironlake_crtc_disable; dev_priv->display.off = ironlake_crtc_off; dev_priv->display.update_plane = ironlake_update_plane; } else { + dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; dev_priv->display.crtc_enable = i9xx_crtc_enable; dev_priv->display.crtc_disable = i9xx_crtc_disable; @@ -9034,14 +9095,10 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, } } - for_each_pipe(pipe) { - crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); - - tmp = I915_READ(PIPECONF(crtc->cpu_transcoder)); - if (tmp & PIPECONF_ENABLE) - crtc->active = true; - else - crtc->active = false; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, + base.head) { + crtc->active = dev_priv->display.get_pipe_config(crtc, + &crtc->config); crtc->base.enabled = crtc->active;