@@ -181,7 +181,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
/* Enable the PCH Receiver FDI PLL */
rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
- FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);
+ FDI_RX_PLL_ENABLE |
+ ((intel_crtc->config.fdi_lanes - 1) << 19);
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
POSTING_READ(_FDI_RXA_CTL);
udelay(220);
@@ -209,7 +210,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
* port reversal bit */
I915_WRITE(DDI_BUF_CTL(PORT_E),
DDI_BUF_CTL_ENABLE |
- ((intel_crtc->fdi_lanes - 1) << 1) |
+ ((intel_crtc->config.fdi_lanes - 1) << 1) |
hsw_ddi_buf_ctl_values[i / 2]);
POSTING_READ(DDI_BUF_CTL(PORT_E));
@@ -1019,7 +1020,7 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
} else if (type == INTEL_OUTPUT_ANALOG) {
temp |= TRANS_DDI_MODE_SELECT_FDI;
- temp |= (intel_crtc->fdi_lanes - 1) << 1;
+ temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
type == INTEL_OUTPUT_EDP) {
@@ -2371,7 +2371,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(7 << 19);
- temp |= (intel_crtc->fdi_lanes - 1) << 19;
+ temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_1;
I915_WRITE(reg, temp | FDI_TX_ENABLE);
@@ -2469,7 +2469,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(7 << 19);
- temp |= (intel_crtc->fdi_lanes - 1) << 19;
+ temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_1;
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2604,7 +2604,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(7 << 19);
- temp |= (intel_crtc->fdi_lanes - 1) << 19;
+ temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2706,7 +2706,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~((0x7 << 19) | (0x7 << 16));
- temp |= (intel_crtc->fdi_lanes - 1) << 19;
+ temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
@@ -5112,12 +5112,12 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
- intel_crtc->pipe, intel_crtc->fdi_lanes);
- if (intel_crtc->fdi_lanes > 4) {
+ intel_crtc->pipe, intel_crtc->config.fdi_lanes);
+ if (intel_crtc->config.fdi_lanes > 4) {
DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
- intel_crtc->pipe, intel_crtc->fdi_lanes);
+ intel_crtc->pipe, intel_crtc->config.fdi_lanes);
/* Clamp lanes to avoid programming the hw with bogus values. */
- intel_crtc->fdi_lanes = 4;
+ intel_crtc->config.fdi_lanes = 4;
return false;
}
@@ -5130,28 +5130,31 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
return true;
case PIPE_B:
if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
- intel_crtc->fdi_lanes > 2) {
+ intel_crtc->config.fdi_lanes > 2) {
DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
- intel_crtc->pipe, intel_crtc->fdi_lanes);
+ intel_crtc->pipe,
+ intel_crtc->config.fdi_lanes);
/* Clamp lanes to avoid programming the hw with bogus values. */
- intel_crtc->fdi_lanes = 2;
+ intel_crtc->config.fdi_lanes = 2;
return false;
}
- if (intel_crtc->fdi_lanes > 2)
+ if (intel_crtc->config.fdi_lanes > 2)
WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
else
cpt_enable_fdi_bc_bifurcation(dev);
return true;
case PIPE_C:
- if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
- if (intel_crtc->fdi_lanes > 2) {
+ if (!pipe_B_crtc->base.enabled ||
+ pipe_B_crtc->config.fdi_lanes <= 2) {
+ if (intel_crtc->config.fdi_lanes > 2) {
DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
- intel_crtc->pipe, intel_crtc->fdi_lanes);
+ intel_crtc->pipe,
+ intel_crtc->config.fdi_lanes);
/* Clamp lanes to avoid programming the hw with bogus values. */
- intel_crtc->fdi_lanes = 2;
+ intel_crtc->config.fdi_lanes = 2;
return false;
}
@@ -5239,7 +5242,7 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
lane = ironlake_get_lanes_required(target_clock, link_bw,
intel_crtc->config.pipe_bpp);
- intel_crtc->fdi_lanes = lane;
+ intel_crtc->config.fdi_lanes = lane;
if (intel_crtc->config.pixel_multiplier > 1)
link_bw *= intel_crtc->config.pixel_multiplier;
@@ -5456,7 +5459,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
/* Note, this also computes intel_crtc->fdi_lanes which is used below in
* ironlake_check_fdi_lanes. */
- intel_crtc->fdi_lanes = 0;
+ intel_crtc->config.fdi_lanes = 0;
if (intel_crtc->config.has_pch_encoder)
ironlake_fdi_set_m_n(crtc);
@@ -222,6 +222,9 @@ struct intel_crtc_config {
int pixel_target_clock;
/* Used by SDVO (and if we ever fix it, HDMI). */
unsigned pixel_multiplier;
+
+ /* FDI lanes used, only valid if has_pch_encoder is set. */
+ int fdi_lanes;
};
struct intel_crtc {
@@ -241,7 +244,6 @@ struct intel_crtc {
bool lowfreq_avail;
struct intel_overlay *overlay;
struct intel_unpin_work *unpin_work;
- int fdi_lanes;
atomic_t unpin_work_count;
We need this for two reasons: - Correct handling of shared fdi lanes on ivb with fastboot. - Handling fdi link bw limits when we only have two fdi lanes by dithering down a bit. Just search&replace in this patch, no functional change at all. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_ddi.c | 7 ++++--- drivers/gpu/drm/i915/intel_display.c | 39 +++++++++++++++++++----------------- drivers/gpu/drm/i915/intel_drv.h | 4 +++- 3 files changed, 28 insertions(+), 22 deletions(-)