diff mbox

[07/28] drm/i915: implement WaForceL3Serialization on VLV and IVB

Message ID 1362172471-7643-8-git-send-email-jbarnes@virtuousgeek.org (mailing list archive)
State New, archived
Headers show

Commit Message

Jesse Barnes March 1, 2013, 9:14 p.m. UTC
References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |    3 +++
 drivers/gpu/drm/i915/intel_pm.c |    4 ++++
 2 files changed, 7 insertions(+)

Comments

Ville Syrjälä March 1, 2013, 9:43 p.m. UTC | #1
On Fri, Mar 01, 2013 at 01:14:10PM -0800, Jesse Barnes wrote:
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    3 +++
>  drivers/gpu/drm/i915/intel_pm.c |    4 ++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 766518b..09b9072 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3583,6 +3583,9 @@
>  #define GEN7_L3SQCREG4				0xb034
>  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
>  
> +#define GEN7_L3SQCREG4				0xb034
> +#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> +
>  /* WaCatErrorRejectionIssue */
>  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
>  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 61fee7f..0f1adc8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3830,6 +3830,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>  		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
>  
> +	/* WaForceL3Serialization */
> +	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> +		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);

I suspect doing it twice won't serialize things any further ;)

Actually it seems we're already clearing the bit twice. So this
is the third one you're adding.

> +
>  	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
>  	 * gating disable must be set.  Failure to set it results in
>  	 * flickering pixels due to Z write ordering failures after
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Jesse Barnes March 1, 2013, 9:58 p.m. UTC | #2
On Fri, 1 Mar 2013 23:43:25 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Fri, Mar 01, 2013 at 01:14:10PM -0800, Jesse Barnes wrote:
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |    3 +++
> >  drivers/gpu/drm/i915/intel_pm.c |    4 ++++
> >  2 files changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 766518b..09b9072 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3583,6 +3583,9 @@
> >  #define GEN7_L3SQCREG4				0xb034
> >  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> >  
> > +#define GEN7_L3SQCREG4				0xb034
> > +#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> > +
> >  /* WaCatErrorRejectionIssue */
> >  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> >  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 61fee7f..0f1adc8 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3830,6 +3830,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >  	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> >  		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> >  
> > +	/* WaForceL3Serialization */
> > +	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> > +		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> 
> I suspect doing it twice won't serialize things any further ;)
> 
> Actually it seems we're already clearing the bit twice. So this
> is the third one you're adding.
> 

Oh good I can drop this one then.
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 766518b..09b9072 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3583,6 +3583,9 @@ 
 #define GEN7_L3SQCREG4				0xb034
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
 
+#define GEN7_L3SQCREG4				0xb034
+#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
+
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61fee7f..0f1adc8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3830,6 +3830,10 @@  static void ivybridge_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
 		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
 
+	/* WaForceL3Serialization */
+	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
+		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
+
 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
 	 * gating disable must be set.  Failure to set it results in
 	 * flickering pixels due to Z write ordering failures after