From patchwork Fri Mar 1 23:38:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenneth Graunke X-Patchwork-Id: 2205271 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id C78013FCF6 for ; Fri, 1 Mar 2013 23:37:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D5AA2E60FF for ; Fri, 1 Mar 2013 15:37:47 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from hapkido.dreamhost.com (hapkido.dreamhost.com [66.33.216.122]) by gabe.freedesktop.org (Postfix) with ESMTP id 52833E5D2C for ; Fri, 1 Mar 2013 15:37:41 -0800 (PST) Received: from homiemail-a62.g.dreamhost.com (caiajhbdcbbj.dreamhost.com [208.97.132.119]) by hapkido.dreamhost.com (Postfix) with ESMTP id 0ED4DDCAB1 for ; Fri, 1 Mar 2013 15:37:41 -0800 (PST) Received: from homiemail-a62.g.dreamhost.com (localhost [127.0.0.1]) by homiemail-a62.g.dreamhost.com (Postfix) with ESMTP id 8351A634075; Fri, 1 Mar 2013 15:37:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=whitecape.org; h=from:to :cc:subject:date:message-id; s=whitecape.org; bh=ao3KVYhRdwW4s9q kncXWCH1K2pg=; b=Cmxcz0jAde3exX8pRWgbtl3bWwnEz/+z0JN0UwyXJdxcFa7 HbinFax1/D4vWTAVTp4m5BKFTzfOgGdAyueENvQug/0HrPnaTZ/yK4m6BhDzIxdB H51NLb6tKBV/TqCl/1Xy3f/q7mfFhGQfV7iyEVaxvIcEhGsjvMveRzz81E3A= Received: from vakarian.amr.corp.intel.com (static-50-43-15-186.bvtn.or.frontiernet.net [50.43.15.186]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: kenneth@whitecape.org) by homiemail-a62.g.dreamhost.com (Postfix) with ESMTPSA id 25DCE63406F; Fri, 1 Mar 2013 15:37:38 -0800 (PST) From: Kenneth Graunke To: intel-gfx@lists.freedesktop.org Date: Fri, 1 Mar 2013 15:38:25 -0800 Message-Id: <1362181105-1834-1-git-send-email-kenneth@whitecape.org> X-Mailer: git-send-email 1.8.1.4 Subject: [Intel-gfx] [libdrm PATCH] intel: Fix Haswell CRW PCI IDs. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke --- intel/intel_chipset.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 3123a90..b65d3ef 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -115,15 +115,15 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ -#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ +#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ #define PCI_CHIP_VALLEYVIEW_1 0x0f31