diff mbox

[19/20] drm/i915/dp: program VSwing and Preemphasis control settings on VLV

Message ID 1362768363-3710-19-git-send-email-jbarnes@virtuousgeek.org (mailing list archive)
State New, archived
Headers show

Commit Message

Jesse Barnes March 8, 2013, 6:46 p.m. UTC 
From: Pallavi G <pallavi.g@intel.com>

Program few Tx buffer Swing control settings through DPIO.

Signed-off-by: Pallavi G <pallavi.g@intel.com>
Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    3 +-
 drivers/gpu/drm/i915/intel_dp.c      |  114 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h     |    2 +
 3 files changed, 115 insertions(+), 4 deletions(-)

Comments

Daniel Vetter March 19, 2013, 7:30 p.m. UTC | #1 
On Fri, Mar 08, 2013 at 10:46:02AM -0800, Jesse Barnes wrote:
> From: Pallavi G <pallavi.g@intel.com>
> 
> Program few Tx buffer Swing control settings through DPIO.
> 
> Signed-off-by: Pallavi G <pallavi.g@intel.com>
> Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>

Two comments below.

> ---
>  drivers/gpu/drm/i915/intel_display.c |    3 +-
>  drivers/gpu/drm/i915/intel_dp.c      |  114 +++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_drv.h     |    2 +
>  3 files changed, 115 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5e338c6..3b085bb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -451,8 +451,7 @@ u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
>  	return I915_READ(DPIO_DATA);
>  }
>  
> -static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> -			     u32 val)
> +void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
>  {
>  	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6a2c606..b2dbd31 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1527,7 +1527,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  
> -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
> +	if (IS_VALLEYVIEW(dev))
> +		return DP_TRAIN_VOLTAGE_SWING_1200;
> +	else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
>  		return DP_TRAIN_VOLTAGE_SWING_800;
>  	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
>  		return DP_TRAIN_VOLTAGE_SWING_1200;
> @@ -1552,7 +1554,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  		default:
>  			return DP_TRAIN_PRE_EMPHASIS_0;
>  		}
> -	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			return DP_TRAIN_PRE_EMPHASIS_9_5;
> +		case DP_TRAIN_VOLTAGE_SWING_600:
> +			return DP_TRAIN_PRE_EMPHASIS_6;
> +		case DP_TRAIN_VOLTAGE_SWING_800:
> +			return DP_TRAIN_PRE_EMPHASIS_3_5;
> +		case DP_TRAIN_VOLTAGE_SWING_1200:
> +		default:
> +			return DP_TRAIN_PRE_EMPHASIS_0;
> +		}
> +	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_400:
>  			return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1577,15 +1591,111 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  	}
>  }
>  
> +static void vlv_set_vswing_pre_emphasis(struct intel_dp *intel_dp, uint8_t v,
> +					uint8_t p)
> +{
> +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long Demph_reg_value, Preemph_reg_value,
> +		Uniqtranscale_reg_value;

CodingStyle doesn't like uppercase in variables.

> +	switch (p) {
> +	case DP_TRAIN_PRE_EMPHASIS_0:
> +		Preemph_reg_value = 0x0004000;
> +		switch (v) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			Demph_reg_value = 0x2B405555;
> +			Uniqtranscale_reg_value = 0x552AB83A;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_600:
> +			Demph_reg_value = 0x2B404040;
> +			Uniqtranscale_reg_value = 0x5548B83A;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_800:
> +			Demph_reg_value = 0x2B245555;
> +			Uniqtranscale_reg_value = 0x5560B83A;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_1200:
> +			Demph_reg_value = 0x2B405555;
> +			Uniqtranscale_reg_value = 0x5598DA3A;
> +			break;
> +		default:
> +			return;
> +		}
> +		break;
> +	case DP_TRAIN_PRE_EMPHASIS_3_5:
> +		Preemph_reg_value = 0x0002000;
> +		switch (v) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			Demph_reg_value = 0x2B404040;
> +			Uniqtranscale_reg_value = 0x5552B83A;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_600:
> +			Demph_reg_value = 0x2B404848;
> +			Uniqtranscale_reg_value = 0x5580B83A;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_800:
> +			Demph_reg_value = 0x2B404040;
> +			Uniqtranscale_reg_value = 0x55ADDA3A;
> +			break;
> +		default:
> +			return;
> +		}
> +		break;
> +	case DP_TRAIN_PRE_EMPHASIS_6:
> +		Preemph_reg_value = 0x0000000;
> +		switch (v) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			Demph_reg_value = 0x2B305555;
> +			Uniqtranscale_reg_value = 0x5570B83A;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_600:
> +			Demph_reg_value = 0x2B2B4040;
> +			Uniqtranscale_reg_value = 0x55ADDA3A;
> +			break;
> +		default:
> +			return;
> +		}
> +		break;
> +	case DP_TRAIN_PRE_EMPHASIS_9_5:
> +		Preemph_reg_value = 0x0006000;
> +		switch (v) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			Demph_reg_value = 0x1B405555;
> +			Uniqtranscale_reg_value = 0x55ADDA3A;
> +			break;
> +		default:
> +			return;
> +		}
> +		break;
> +	default:
> +		return;
> +	}
> +
> +	/* eDP is only on port C */
> +	mutex_lock(&dev_priv->dpio_lock);
> +	intel_dpio_write(dev_priv, 0x8494, 0x00000000);
> +	intel_dpio_write(dev_priv, 0x8490, Demph_reg_value);
> +	intel_dpio_write(dev_priv, 0x8488, Uniqtranscale_reg_value);
> +	intel_dpio_write(dev_priv, 0x848c, 0x0C782040);
> +	intel_dpio_write(dev_priv, 0x842c, 0x00030000);
> +	intel_dpio_write(dev_priv, 0x8424, Preemph_reg_value);
> +	intel_dpio_write(dev_priv, 0x8494, 0x80000000);
> +	mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
>  static void
>  intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
>  {
> +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	uint8_t v = 0;
>  	uint8_t p = 0;
>  	int lane;
>  	uint8_t voltage_max;
>  	uint8_t preemph_max;
>  
> +	if (IS_VALLEYVIEW(dev))
> +		vlv_set_vswing_pre_emphasis(intel_dp, v, p);

This call should be moved to intel_dp_set_signal_levels I think. Bspec has
similar registers for some special voltage/pre-emph settings on other
platforms, so we might need to add other code like that.
-Daniel

> +
>  	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>  		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>  		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 494037d..03fdfbd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -661,6 +661,8 @@ extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
>  				     struct drm_file *file_priv);
>  
>  extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
> +extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> +			     u32 val);
>  
>  /* Power-related functions, located in intel_pm.c */
>  extern void intel_init_pm(struct drm_device *dev);
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5e338c6..3b085bb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -451,8 +451,7 @@  u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 	return I915_READ(DPIO_DATA);
 }
 
-static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
-			     u32 val)
+void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 {
 	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6a2c606..b2dbd31 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1527,7 +1527,9 @@  intel_dp_voltage_max(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
-	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
+	if (IS_VALLEYVIEW(dev))
+		return DP_TRAIN_VOLTAGE_SWING_1200;
+	else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
 		return DP_TRAIN_VOLTAGE_SWING_800;
 	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
 		return DP_TRAIN_VOLTAGE_SWING_1200;
@@ -1552,7 +1554,19 @@  intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPHASIS_0;
 		}
-	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev)) {
+		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			return DP_TRAIN_PRE_EMPHASIS_9_5;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			return DP_TRAIN_PRE_EMPHASIS_6;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			return DP_TRAIN_PRE_EMPHASIS_3_5;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+		default:
+			return DP_TRAIN_PRE_EMPHASIS_0;
+		}
+	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_400:
 			return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1577,15 +1591,111 @@  intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 	}
 }
 
+static void vlv_set_vswing_pre_emphasis(struct intel_dp *intel_dp, uint8_t v,
+					uint8_t p)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long Demph_reg_value, Preemph_reg_value,
+		Uniqtranscale_reg_value;
+	switch (p) {
+	case DP_TRAIN_PRE_EMPHASIS_0:
+		Preemph_reg_value = 0x0004000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B405555;
+			Uniqtranscale_reg_value = 0x552AB83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x5548B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			Demph_reg_value = 0x2B245555;
+			Uniqtranscale_reg_value = 0x5560B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+			Demph_reg_value = 0x2B405555;
+			Uniqtranscale_reg_value = 0x5598DA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_3_5:
+		Preemph_reg_value = 0x0002000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x5552B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B404848;
+			Uniqtranscale_reg_value = 0x5580B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_6:
+		Preemph_reg_value = 0x0000000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B305555;
+			Uniqtranscale_reg_value = 0x5570B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B2B4040;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_9_5:
+		Preemph_reg_value = 0x0006000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x1B405555;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	default:
+		return;
+	}
+
+	/* eDP is only on port C */
+	mutex_lock(&dev_priv->dpio_lock);
+	intel_dpio_write(dev_priv, 0x8494, 0x00000000);
+	intel_dpio_write(dev_priv, 0x8490, Demph_reg_value);
+	intel_dpio_write(dev_priv, 0x8488, Uniqtranscale_reg_value);
+	intel_dpio_write(dev_priv, 0x848c, 0x0C782040);
+	intel_dpio_write(dev_priv, 0x842c, 0x00030000);
+	intel_dpio_write(dev_priv, 0x8424, Preemph_reg_value);
+	intel_dpio_write(dev_priv, 0x8494, 0x80000000);
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void
 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	uint8_t v = 0;
 	uint8_t p = 0;
 	int lane;
 	uint8_t voltage_max;
 	uint8_t preemph_max;
 
+	if (IS_VALLEYVIEW(dev))
+		vlv_set_vswing_pre_emphasis(intel_dp, v, p);
+
 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
 		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 494037d..03fdfbd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -661,6 +661,8 @@  extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 				     struct drm_file *file_priv);
 
 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
+extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
+			     u32 val);
 
 /* Power-related functions, located in intel_pm.c */
 extern void intel_init_pm(struct drm_device *dev);