From patchwork Thu Mar 28 15:38:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2357281 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 69D17DF2A1 for ; Thu, 28 Mar 2013 15:37:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 51C21E5DB9 for ; Thu, 28 Mar 2013 08:37:20 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f176.google.com (mail-ea0-f176.google.com [209.85.215.176]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CA46E5E9E for ; Thu, 28 Mar 2013 08:35:22 -0700 (PDT) Received: by mail-ea0-f176.google.com with SMTP id h10so4110929eaj.21 for ; Thu, 28 Mar 2013 08:35:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=8VT1XT5VrDoTYhXPhL4AFDBnjeBVnnkR2P4ZHHzZgtI=; b=QQsAGztOiGkCqJzbQ1xAOSL7PVpz0fKjhKK35D9U3LEcTGaz/XYm7I5vZaGmVZZYI5 S/2w5DXcZCKRCAWLYyOaTNIaYzwlYn+hkACyBJGmhNSjlCPUKRxWl3v6EAL8gJQqK6U6 nXUzAU0qpCzqnspHEkVamCg1E9dsSHY1byeDE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=8VT1XT5VrDoTYhXPhL4AFDBnjeBVnnkR2P4ZHHzZgtI=; b=d2Wh5mEYtChgxrj89rvaddPANVf+L1yCyj1NqIkoMX19H54RFDl4dB0Xvl9z4dDeNW 3im5PJialF20fBVtqkV+VbRjByWIzSGuLx5yg932Uq/XSjoyX/5N7rJNi28lbqf8aOrV nqKYiGnVAvOXcu68SmLLjTI0+OaMq0jF5l4kRAZizlzf6cBwbHp5sLoYTriYkmAOXdo3 spOC4OfqJjw8JMV6Q/UjLfonRUYPwAxU22MmBePEOv1LlE2sNUKems/5vudrMLfvbdTJ iSOLqD/7bN3caKkuht7dk8sxboT03qDVy2+OrK7FIYCJbpUQUzCCGCRR7Y2putA2rNpD RKtg== X-Received: by 10.14.210.132 with SMTP id u4mr67664226eeo.19.1364484922278; Thu, 28 Mar 2013 08:35:22 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id r4sm38425473eeo.12.2013.03.28.08.35.20 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 28 Mar 2013 08:35:21 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 28 Mar 2013 16:38:08 +0100 Message-Id: <1364485088-12684-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <20130328151303.GO4469@intel.com> References: <20130328151303.GO4469@intel.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQk7Lq9tF1GnzZtFTkvAByjYkeGtoF7vqufqc5yZCLPqxbyzn/hBOSOW8vue8Yk5cqSQy06G Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: fixup fb bpp computation in pipe_config_set_bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Ville pointed out that my assumption that no unsupported pixel format can get past the pipe config computation stage to the platform update_plane callbacks is wrong. The reason is that this function still checks the old fb->depth value instead of the new pixel_format. While checking with all the other places that use this I've noticed that intel_framebuffer_init already has all the platform checks we need, so replace those checks with a WARN_ON. Since fb->depth isn't set for YUV pixel formats and since we already can't create an fb with an rgb layout not support on the running platform I /think/ this patch doesn't fix any bug. But it surely looks better! v2: BGR formats are also only gen4+, so add the corresponding WARN_ON, too (Ville). Cc: Ville Syrjälä Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3f3a3dc..5e8b91f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7394,23 +7394,34 @@ pipe_config_set_bpp(struct drm_crtc *crtc, struct drm_connector *connector; int bpp; - switch (fb->depth) { - case 8: + switch (fb->pixel_format) { + case DRM_FORMAT_C8: bpp = 8*3; /* since we go through a colormap */ break; - case 15: - case 16: + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_ARGB1555: + /* checked in intel_framebuffer_init already */ + if (WARN_ON(INTEL_INFO(dev)->gen > 3)) + return -EINVAL; + case DRM_FORMAT_RGB565: bpp = 6*3; /* min is 18bpp */ break; - case 24: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + /* checked in intel_framebuffer_init already */ + if (WARN_ON(INTEL_INFO(dev)->gen < 4)) + return -EINVAL; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: bpp = 8*3; break; - case 30: - if (INTEL_INFO(dev)->gen < 4) { - DRM_DEBUG_KMS("10 bpc not supported on gen2/3\n"); + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + /* checked in intel_framebuffer_init already */ + if (WARN_ON(INTEL_INFO(dev)->gen < 4)) return -EINVAL; - } - bpp = 10*3; break; /* TODO: gen4+ supports 16 bpc floating point, too. */