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[2/3] drm/i915: Set PIPECONF color range bit on Valleyview

Message ID 1364908210-13748-3-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä April 2, 2013, 1:10 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Jani Nikula April 3, 2013, 10:11 a.m. UTC | #1 
On Tue, 02 Apr 2013, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> VLV has the color range selection bit in the PIPECONF register.
> Configure it appropriately.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dfaea15..e49d86a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4575,6 +4575,13 @@ static void i9xx_set_pipeconf(struct drm_crtc *crtc,
>  	else
>  		pipeconf |= PIPECONF_PROGRESSIVE;
>  
> +	if (IS_VALLEYVIEW(dev)) {
> +		if (intel_crtc->config.limited_color_range)
> +			pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
> +		else
> +			pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
> +	}
> +
>  	I915_WRITE(PIPECONF(pipe), pipeconf);
>  	POSTING_READ(PIPECONF(pipe));
>  }
> -- 
> 1.8.1.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dfaea15..e49d86a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4575,6 +4575,13 @@  static void i9xx_set_pipeconf(struct drm_crtc *crtc,
 	else
 		pipeconf |= PIPECONF_PROGRESSIVE;
 
+	if (IS_VALLEYVIEW(dev)) {
+		if (intel_crtc->config.limited_color_range)
+			pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
+		else
+			pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
+	}
+
 	I915_WRITE(PIPECONF(pipe), pipeconf);
 	POSTING_READ(PIPECONF(pipe));
 }