From patchwork Tue Apr 2 17:03:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 2379591 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 84DDD3FDDA for ; Tue, 2 Apr 2013 17:13:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72071E5DDD for ; Tue, 2 Apr 2013 10:13:18 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy5-pub.bluehost.com (oproxy5-pub.bluehost.com [67.222.38.55]) by gabe.freedesktop.org (Postfix) with SMTP id E6E85E5CB4 for ; Tue, 2 Apr 2013 10:11:28 -0700 (PDT) Received: (qmail 2903 invoked by uid 0); 2 Apr 2013 17:11:27 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy2.bluehost.com with SMTP; 2 Apr 2013 17:11:27 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=uT2+kYAc7wKcUGo007+VPArXMR87b/zBokMoTvC84Cw=; b=pH2N0frPPepJcSZNHcSsbUQb3YAaTc1uNyWkEEbZTih3lZeX9V/0lPXXZFBG4nlFsqkYy+3xTsV0P4EVrbCNUMwYzJSTl9QNSFGmuGZqnKYtAyA2daxXYA5AuAOTHyBe; Received: from [67.161.37.189] (port=54872 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1UN4dC-0006iJ-OU for intel-gfx@lists.freedesktop.org; Tue, 02 Apr 2013 11:04:22 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Tue, 2 Apr 2013 10:03:54 -0700 Message-Id: <1364922237-3620-11-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1364922237-3620-1-git-send-email-jbarnes@virtuousgeek.org> References: <1364922237-3620-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 10/13] drm/i915: fetch PCH PLL state at init time X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We need to properly track PCH PLL sharing configs, and generally set up PCH PLL state at init time as part of the state readout process. I-told-you-so-by: Daniel Vetter Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8b55427..208dde4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6915,6 +6915,54 @@ static int ironlake_crtc_clock_get(struct drm_crtc *crtc) return clock; } +static bool ironlake_crtc_pll_get(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = crtc->dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + u32 dpll_sel; + + if (HAS_PCH_IBX(dev_priv->dev)) + intel_crtc->pch_pll = &dev_priv->pch_plls[intel_crtc->pipe]; + + if (HAS_PCH_CPT(dev_priv->dev)) { + dpll_sel = I915_READ(PCH_DPLL_SEL); + + switch (intel_crtc->pipe) { + case PIPE_A: + if ((dpll_sel & TRANSA_DPLL_ENABLE) && + (dpll_sel & TRANSA_DPLLB_SEL)) + intel_crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSA_DPLL_ENABLE) + intel_crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + case PIPE_B: + if ((dpll_sel & TRANSB_DPLL_ENABLE) && + (dpll_sel & TRANSB_DPLLB_SEL)) + intel_crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSB_DPLL_ENABLE) + intel_crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + case PIPE_C: + if ((dpll_sel & TRANSC_DPLL_ENABLE) && + (dpll_sel & TRANSC_DPLLB_SEL)) + intel_crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSC_DPLL_ENABLE) + intel_crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + default: + break; + } + } + + if (intel_crtc->pch_pll) { + intel_crtc->pch_pll->refcount++; + intel_crtc->pch_pll->active = 1; + return true; + } + + return false; +} + static bool ironlake_crtc_get_mode(struct drm_crtc *crtc, struct drm_display_mode *mode) { @@ -6943,6 +6991,9 @@ static bool ironlake_crtc_get_mode(struct drm_crtc *crtc, mode->clock = ironlake_crtc_clock_get(crtc); + if (!ironlake_crtc_pll_get(crtc)) + return false; + drm_mode_set_name(mode); return true;