From patchwork Thu Apr 4 15:19:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2393271 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 946633FD1A for ; Thu, 4 Apr 2013 15:17:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7374DE643B for ; Thu, 4 Apr 2013 08:17:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f47.google.com (mail-ee0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTP id EC28EE6462 for ; Thu, 4 Apr 2013 08:16:42 -0700 (PDT) Received: by mail-ee0-f47.google.com with SMTP id t10so1065896eei.34 for ; Thu, 04 Apr 2013 08:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=UxJ5/gWACe4YsoLohTjBdX7kE6w0HP1+n2LTOVeD920=; b=j7C5p2Dte4iOySU+jxAZMpVKh/++TqJQDI9Fv+NnBuBlHGFP4VxojvXdCf47bKAnDK ETlSuorGZQVA3ywhAPddcuGRCOINJWcNIub76nlF7koTIRuYAl6CS5mw2F3LffjKg4Im c5+vKJh4mVYkSyUnzENWVh5VvqcwhZTz8kGnE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=UxJ5/gWACe4YsoLohTjBdX7kE6w0HP1+n2LTOVeD920=; b=V0I8UKMatoHJ52i7A/PhcmWPDmjweyR8Mj5c2IOGPfsHud3yUNCBdCrbW2oYes66wL 1EhUx5WN8PmFUqS/gvRkRYN2ZugwIsI2JJUKW+6WGx0o+3GsuumOr3DzQKnDGGCgxssN HCWpprsgtIT/HD2tCJLSkSEJ0CW/Ymau6vUTBolktmBqpSRPPntyw0MeNQi5N6aRwwER VziB6xU0SZjzNKAzZZA8EBpCadx/UonYUk04GxYPZj97sahwkE23JtQejlfdkn75iFUg azmtQUcwI08oa3ZCsYIcRRVhf0flzPPKQq0CjBknbCI0F7l2q5tZEOfSxsAKQBM1WQD5 2MCA== X-Received: by 10.14.216.2 with SMTP id f2mr11631408eep.44.1365088602075; Thu, 04 Apr 2013 08:16:42 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id r4sm11545060eeo.12.2013.04.04.08.16.40 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 04 Apr 2013 08:16:41 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 4 Apr 2013 17:19:37 +0200 Message-Id: <1365088777-5358-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQmKeRkc2EiE0BFcNFrVmieOE4OQRAiT6XEy+jrmrmCAOXaxCc2FVTYBCt6SSr3rXm6RPRhP Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: revert eDP bpp clamping code changes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The behaviour around handling the eDP bpp value from vbt has been slightly changed in commit 3600836585e3fdef0a1410d63fe5ce4015007aac Author: Daniel Vetter Date: Wed Mar 27 00:44:59 2013 +0100 drm/i915: convert DP autodither code to new infrastructure The old behaviour was that we used the plane's bpp (usually 24bpp) for computing the dp link bw, but set up the pipe with the bpp value from vbt if available. The takes the vbt bpp override into account even for the dp link bw configuration. On Paulo's hsw machine this resulted in a slower link clock and a black screen - but the mode actually /should/ fit even with the lower clock. Until we've cleared up simply stay bug-for-bug compatible with the old code. While at it, also restore a debug message lost in: commit 4e53c2e010e531b4a014692199e978482d471c7e Author: Daniel Vetter Date: Wed Mar 27 00:44:58 2013 +0100 drm/i915: precompute pipe bpp before touching the hw Cc: Paulo Zanoni Signed-off-by: Daniel Vetter Reviewed-by: Paulo Zanoni Tested-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c5cfec3..658d071 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -741,9 +741,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, /* Walk through all bpp values. Luckily they're all nicely spaced with 2 * bpc in between. */ bpp = min_t(int, 8*3, pipe_config->pipe_bpp); - if (is_edp(intel_dp) && dev_priv->edp.bpp) - bpp = min_t(int, bpp, dev_priv->edp.bpp); - for (; bpp >= 6*3; bpp -= 2*3) { mode_rate = intel_dp_link_required(target_clock, bpp); @@ -781,7 +778,6 @@ found: intel_dp->link_bw = bws[clock]; intel_dp->lane_count = lane_count; adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); - pipe_config->pipe_bpp = bpp; pipe_config->pixel_target_clock = target_clock; DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", @@ -796,6 +792,20 @@ found: intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); + /* + * XXX: We have a strange regression where using the vbt edp bpp value + * for the link bw computation results in black screens, the panel only + * works when we do the computation at the usual 24bpp (but still + * requires us to use 18bpp. Until that's fully debugged, stay + * bug-for-bug compatible with the old code. + */ + if (is_edp(intel_dp) && dev_priv->edp.bpp) { + DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", + bpp, dev_priv->edp.bpp); + bpp = min_t(int, bpp, dev_priv->edp.bpp); + } + pipe_config->pipe_bpp = bpp; + return true; }