diff mbox

drm/i915: use lower aux clock divider on non-ULT HSW

Message ID 1365451258-25493-1-git-send-email-jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jani Nikula April 8, 2013, 8 p.m. UTC
Workaround to avoid intermittent aux channel failures, per spec change.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

---

Untested.
---
 drivers/gpu/drm/i915/intel_dp.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Paulo Zanoni April 8, 2013, 9:03 p.m. UTC | #1
Hi

2013/4/8 Jani Nikula <jani.nikula@intel.com>:
> Workaround to avoid intermittent aux channel failures, per spec change.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Untested.
> ---
>  drivers/gpu/drm/i915/intel_dp.c |    5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 482b5e5..5fec183 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -344,7 +344,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>          * Note that PCH attached eDP panels should use a 125MHz input
>          * clock divider.
>          */
> -       if (is_cpu_edp(intel_dp)) {
> +       if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> +               /* Workaround for non-ULT HSW */
> +               aux_clock_divider = 74;
> +       } else if (is_cpu_edp(intel_dp)) {

Your patch will affect the CPU DP AUX too, but it should only affect
the PCH DP AUX registers. You should move this to the !is_cpu_edp
case.

>                 if (HAS_DDI(dev))
>                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
>                 else if (IS_VALLEYVIEW(dev))
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
Paulo Zanoni
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 482b5e5..5fec183 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -344,7 +344,10 @@  intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * Note that PCH attached eDP panels should use a 125MHz input
 	 * clock divider.
 	 */
-	if (is_cpu_edp(intel_dp)) {
+	if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+		/* Workaround for non-ULT HSW */
+		aux_clock_divider = 74;
+	} else if (is_cpu_edp(intel_dp)) {
 		if (HAS_DDI(dev))
 			aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 		else if (IS_VALLEYVIEW(dev))