From patchwork Mon Apr 8 21:49:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2412001 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id A76D2DFB78 for ; Mon, 8 Apr 2013 21:50:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97891E6198 for ; Mon, 8 Apr 2013 14:50:48 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f173.google.com (mail-gh0-f173.google.com [209.85.160.173]) by gabe.freedesktop.org (Postfix) with ESMTP id B77C1E617A for ; Mon, 8 Apr 2013 14:50:00 -0700 (PDT) Received: by mail-gh0-f173.google.com with SMTP id g16so984295ghb.18 for ; Mon, 08 Apr 2013 14:50:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=YZ1vcb4CMAAi8EGzTJ4uQUNFVqJBafaDBbodoRTELYA=; b=qzoiKcHNfgw1Ec6zIcVCx/dhIpD9Wr/Yl/9u36njxobfm/DUCo6yinhAsY1OWCPnZI paSp3eC4TLeyT8+TMjirsqs580GDF5QySHl0P3hIKOsD4dFfvvHHrS7iUJeo4hsIgjdn uLmWwvL5FRzhL0imfW3SG8cGDLKDTs4Q9MF95rhmEe8rxC/IMbfOlhxcVDwwGeMg4CTI r86/iwKZg3M7sXPmgFmBSmHVKZO8JweENkT7Qvmx/3aINzKGAIDdq7fzCI6MIyqHjjTC oPFjVdOfPFRcT9RwYMeJQbbMJ7b2wzG9pkZDHUNZgARjWt1MK1CeJlwBdDc13UxvNt3f NkyA== X-Received: by 10.236.86.105 with SMTP id v69mr13582439yhe.17.1365457800208; Mon, 08 Apr 2013 14:50:00 -0700 (PDT) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPS id t27sm39794904yhm.20.2013.04.08.14.49.58 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 08 Apr 2013 14:49:59 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 8 Apr 2013 18:49:42 -0300 Message-Id: <1365457784-3412-2-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1365457784-3412-1-git-send-email-rodrigo.vivi@gmail.com> References: <1365457784-3412-1-git-send-email-rodrigo.vivi@gmail.com> Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Enable FBC at Haswell. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This patch introduce Frame Buffer Compression (FBC) support for HSW. It adds a new function haswell_enable_fbc to avoid getting ironlake_enable_fbc messed with many IS_HASWELL checks. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 0cfc778..88fd6fb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -291,6 +291,7 @@ static const struct intel_device_info intel_haswell_m_info = { GEN7_FEATURES, .is_haswell = 1, .is_mobile = 1, + .has_fbc = 1, }; static const struct pci_device_id pciidlist[] = { /* aka */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5e91fbb..cb8e213 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -849,6 +849,12 @@ #define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104 +/* Framebuffer compression for Haswell */ +#define HSW_FBC_RT_BASE 0x7020 +#define HSW_FBC_RT_BASE_ADDR_SHIFT 12 + +#define HSW_DPFC_CTL_FENCE_EN (1<<28) +#define HSW_DPFC_CTL_DISABLE_SLB_INIT (1<<15) /* * GPIO regs diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 27f94cd..94e1c3a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -253,6 +253,43 @@ static bool ironlake_fbc_enabled(struct drm_device *dev) return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; } +static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long interval) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_framebuffer *fb = crtc->fb; + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); + struct drm_i915_gem_object *obj = intel_fb->obj; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; + unsigned long stall_watermark = 200; + u32 dpfc_ctl; + + dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); + dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); + dpfc_ctl |= (HSW_DPFC_CTL_FENCE_EN | obj->fence_reg); + dpfc_ctl |= HSW_DPFC_CTL_DISABLE_SLB_INIT; + I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | + (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | + (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); + I915_WRITE(HSW_FBC_RT_BASE, + obj->gtt_offset << HSW_FBC_RT_BASE_ADDR_SHIFT | + ILK_FBC_RT_VALID); + /* enable it... */ + I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); + + if (obj->fence_reg != I915_FENCE_REG_NONE) { + I915_WRITE(SNB_DPFC_CTL_SA, + SNB_CPU_FENCE_ENABLE | obj->fence_reg); + I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); + } else + I915_WRITE(SNB_DPFC_CTL_SA, ~SNB_CPU_FENCE_ENABLE); + + sandybridge_blit_fbc_update(dev); + + DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); +} + bool intel_fbc_enabled(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4158,7 +4195,12 @@ void intel_init_pm(struct drm_device *dev) if (I915_HAS_FBC(dev)) { if (HAS_PCH_SPLIT(dev)) { dev_priv->display.fbc_enabled = ironlake_fbc_enabled; - dev_priv->display.enable_fbc = ironlake_enable_fbc; + if (IS_HASWELL(dev)) + dev_priv->display.enable_fbc = + haswell_enable_fbc; + else + dev_priv->display.enable_fbc = + ironlake_enable_fbc; dev_priv->display.disable_fbc = ironlake_disable_fbc; } else if (IS_GM45(dev)) { dev_priv->display.fbc_enabled = g4x_fbc_enabled;