diff mbox

[i-g-t,1/3] tests/gem_fenced_exec_thrash: Increase MAX_FENCES to 32

Message ID 1365510339-10576-2-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä April 9, 2013, 12:25 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

IVB+ supports 32 fence registers, bump the maximum in the test.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tests/gem_fenced_exec_thrash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Chris Wilson April 9, 2013, 1:05 p.m. UTC | #1 
On Tue, Apr 09, 2013 at 03:25:37PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> IVB+ supports 32 fence registers, bump the maximum in the test.

Then again the test is only relevant for gen2/3 (and 1), and I don't
forsee the use of fences for GPU surface tiling being resurrected. On
the other hand, the test makes sure that future gpus ignore the old
restrictions.

One feature request for the test: feed in > max_fences expect
ENOSPC/EDEADLCK on gen2/3.
-Chris
diff mbox

Patch

diff --git a/tests/gem_fenced_exec_thrash.c b/tests/gem_fenced_exec_thrash.c
index 8281449..b17eba2 100644
--- a/tests/gem_fenced_exec_thrash.c
+++ b/tests/gem_fenced_exec_thrash.c
@@ -45,7 +45,7 @@ 
 
 #define BATCH_SIZE 4096
 
-#define MAX_FENCES 16
+#define MAX_FENCES 32
 
 #define MI_BATCH_BUFFER_END	(0xA<<23)