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[2/3] drm/i915: RC6 Fix Write Min Frequency Table.

Message ID 1365543166-7051-3-git-send-email-rodrigo.vivi@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rodrigo Vivi April 9, 2013, 9:32 p.m. UTC
According to SNB GT PM Programming Guide page 9,
Write Min Frequency Table is 09h

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Chris Wilson April 10, 2013, 9:23 a.m. UTC | #1
On Tue, Apr 09, 2013 at 06:32:45PM -0300, Rodrigo Vivi wrote:
> According to SNB GT PM Programming Guide page 9,
> Write Min Frequency Table is 09h

I think this is the winner of what workarounds the hang...
(Since patch 3 is a no-op, patch 1 still reverts a change to the media
turbo mode requested by VPG.)

The original code for this patch is correct, I have in the bspec:

0x8 WRITE_MIN_FREQ_TABLE
0x9 READ_MIN_FREQ_TABLE

So the effect of this patch is to undo the ring/uncore scaling with GPU
frequency which will slow everything down and is less likely to provoke
uncore death.
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc4f542f..5dcc09e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4305,7 +4305,7 @@ 
 #define GEN6_PCODE_MAILBOX			0x138124
 #define   GEN6_PCODE_READY			(1<<31)
 #define   GEN6_READ_OC_PARAMS			0xc
-#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x9
 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
 #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
 #define	  GEN6_PCODE_READ_RC6VIDS		0x5