| Message ID | 1365623111-3133-1-git-send-email-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Apr 10, 2013 at 08:45:11PM +0100, Chris Wilson wrote: > Haswell introduces a separate frequency domain for the ring (uncore). So > where we used to increase the CPU (IA) clock with GPU busyness, we now > need to scale the ring frequency directly instead. As the ring limits > our memory bandwidth, it is vital for performance that when the GPU is > busy, we increase the frequency of the ring to increase the available > memory bandwidth. > > v2: Fix the algorithm to actually use the scaled gpu frequency for the ring. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Jesse Barnes <jbarnes@virtuousgeek.org> I think this is another reason to split hsw rps code from snb/ivb. I think I'll wait until Rodrigo's patch is in, and then apply this. Call me a scared chicken, but I kinda am wrt rps stuff ;-) -Daniel
On Wed, 10 Apr 2013 20:45:11 +0100 Chris Wilson <chris@chris-wilson.co.uk> wrote: > + ring_freq = (gpu_freq * 5 + 3) / 4; > + ring_freq = max(max_ring_freq, ring_freq); Should this be min(max_ring_freq, ring_freq)? Otherwise it seems like every ia_freq will correspond to the highest ring freq. Also, where are you setting ia_freq in the HSW case? Looks like it'll be 0? I guess that means we just need the gpu and ring freq correlation on HSW, but that reinforces Daniel's point that a separate function would probably be clearer. Or you could update the changelog with "scale the ring frequency directly with the GPU frequency" or something.
On Wed, Apr 10, 2013 at 02:41:39PM -0700, Jesse Barnes wrote: > On Wed, 10 Apr 2013 20:45:11 +0100 > Chris Wilson <chris@chris-wilson.co.uk> wrote: > > > + ring_freq = (gpu_freq * 5 + 3) / 4; > > + ring_freq = max(max_ring_freq, ring_freq); > > Should this be min(max_ring_freq, ring_freq)? Otherwise it seems like > every ia_freq will correspond to the highest ring freq. s/max_ring_freq/min_ring_freq/, bad name in retrospect. The algorithm is drawn from the pm guide so that the ring is always running at least as fast as memory whilst the gpu is active, and then scales up cache bandwidth as the gpu gets busier and faster. By that formula, only the first few GPU freqs run the ring at the recommended minimum frequency. > Also, where are you setting ia_freq in the HSW case? Looks like it'll > be 0? Right. Again the guide says to not abitrarily raise the CPU frequencies, which makes sense as cpufreq will raise those itself based on demand. > I guess that means we just need the gpu and ring freq > correlation on HSW, but that reinforces Daniel's point that a separate > function would probably be clearer. Or you could update the changelog > with "scale the ring frequency directly with the GPU frequency" or > something. If you look at the changelog, it uses those very terms. :-p -Chris
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7da45aa..6220d97 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1357,7 +1357,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) if (ret) return ret; - seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); + seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); for (gpu_freq = dev_priv->rps.min_delay; gpu_freq <= dev_priv->rps.max_delay; @@ -1366,7 +1366,10 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_MIN_FREQ_TABLE, &ia_freq); - seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100); + seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", + gpu_freq * GT_FREQUENCY_MULTIPLIER, + ((ia_freq >> 0) & 0xff) * 100, + ((ia_freq >> 8) & 0xff) * 100); } mutex_unlock(&dev_priv->rps.hw_lock); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e0fc070..077d40f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1210,6 +1210,9 @@ #define MCHBAR_MIRROR_BASE_SNB 0x140000 +/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ +#define DCLK 0x5e04 + /** 915-945 and GM965 MCH register controlling DRAM channel access */ #define DCC 0x10200 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) @@ -4390,6 +4393,7 @@ #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) #define GEN6_PCODE_DATA 0x138128 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 +#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 #define VLV_IOSF_DOORBELL_REQ 0x182100 #define IOSF_DEVFN_SHIFT 24 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index baea4fc..89746e1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2684,8 +2684,8 @@ static void gen6_update_ring_freq(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; int min_freq = 15; - int gpu_freq; - unsigned int ia_freq, max_ia_freq; + unsigned int gpu_freq; + unsigned int max_ia_freq, max_ring_freq; int scaling_factor = 180; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -2701,6 +2701,10 @@ static void gen6_update_ring_freq(struct drm_device *dev) /* Convert from kHz to MHz */ max_ia_freq /= 1000; + max_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK); + /* convert DDR frequency from units of 133.3MHz to bandwidth */ + max_ring_freq = (2 * 4 * max_ring_freq + 2)/ 3; + /* * For each potential GPU frequency, load a ring frequency we'd like * to use for memory access. We do this by specifying the IA frequency @@ -2709,21 +2713,28 @@ static void gen6_update_ring_freq(struct drm_device *dev) for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; gpu_freq--) { int diff = dev_priv->rps.max_delay - gpu_freq; - - /* - * For GPU frequencies less than 750MHz, just use the lowest - * ring freq. - */ - if (gpu_freq < min_freq) - ia_freq = 800; - else - ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); - ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); - ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT; + unsigned int ia_freq = 0, ring_freq = 0; + + if (IS_HASWELL(dev)) { + ring_freq = (gpu_freq * 5 + 3) / 4; + ring_freq = max(max_ring_freq, ring_freq); + } else { + /* + * For GPU frequencies less than 750MHz, + * just use the lowest ring freq. + */ + if (gpu_freq < min_freq) + ia_freq = 800; + else + ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); + ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); + } sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, - ia_freq | gpu_freq); + ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | + ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | + gpu_freq); } }
Haswell introduces a separate frequency domain for the ring (uncore). So where we used to increase the CPU (IA) clock with GPU busyness, we now need to scale the ring frequency directly instead. As the ring limits our memory bandwidth, it is vital for performance that when the GPU is busy, we increase the frequency of the ring to increase the available memory bandwidth. v2: Fix the algorithm to actually use the scaled gpu frequency for the ring. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++-- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_pm.c | 39 ++++++++++++++++++++++------------- 3 files changed, 34 insertions(+), 16 deletions(-)