From patchwork Thu Apr 11 14:29:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2429011 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id F264ADF230 for ; Thu, 11 Apr 2013 14:33:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA27EE6637 for ; Thu, 11 Apr 2013 07:33:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B17FE6623 for ; Thu, 11 Apr 2013 07:30:55 -0700 (PDT) Received: by mail-ea0-f172.google.com with SMTP id z7so800330eaf.3 for ; Thu, 11 Apr 2013 07:30:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=qZyHvlg3gazw7vyKjRBWug51fwSACurwZIHA92an58c=; b=NtRlYAGsAzSTwyn6zd8vcEX5PtF5snlzde302Ja1MPfLgVrlUsJpiDfXxYx5gh/+DQ kqh3UgvAFMUEmEZNKfFo911Hm3AmY82JCxzQQLL5Zy+X0rOP5Yt4QwqIHNXoTAoymXtn TOnoYQ0t+1jKFudpwzI57SaDyXN9sqsObvNO0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=qZyHvlg3gazw7vyKjRBWug51fwSACurwZIHA92an58c=; b=dUbjh3GQf08h+FvjOPyTnimB71z/+JQAQjJjv75oIv+D7cONs0aw1Xjpae+HF7dL9P ZVeYYf83fLj8VjJJqY0XgV+bHADYo9e3xDqU4XQlErEw1Gy1KwABy1wGJsM0GKcBhQeY vUMGp3B3apWCJVsm5Mp2Fw7Vkjko5l7vN6ey9lnu48QXJF2poPcvjbz2guRoz8mv/c+j 11GlB5XJewMrLjvKB+Xhe9WAVlIW0jB/ei2g8SNLnnDNN1ipW4u3jH0Qg4D88ZC5IvUU 9d1MJ0R2hK/qXm4BhYxSVeLAYMmjgbEQd1UxYsq/WpwwkOw22ysStaoT3K/z5zUuQPog OpTA== X-Received: by 10.14.210.132 with SMTP id u4mr17554670eeo.19.1365690654257; Thu, 11 Apr 2013 07:30:54 -0700 (PDT) Received: from gina.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id a41sm5965845eei.4.2013.04.11.07.30.52 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Apr 2013 07:30:53 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 11 Apr 2013 16:29:09 +0200 Message-Id: <1365690550-5716-6-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1365690550-5716-1-git-send-email-daniel.vetter@ffwll.ch> References: <1365690550-5716-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQnaWm4zuaMkHbsJNex56paglSE/GVxxsQumTZ4erLSqOlbqTfIkMOeV6BiZs+RRxnNFzacV Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 6/7] drm/i915: add pipe asserts for the crtc enable sequence X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The i9xx modeset sequence is currently pretty fishy, so tight it all up with some good assert-sprinkling. We already have good coverage on the disable side, but the enable side is spotty (since until recently it was wrong). Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e91e01c..0941159 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1379,6 +1379,8 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) int reg; u32 val; + assert_pipe_disabled(dev_priv, pipe); + /* No really, not for ILK+ */ BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); @@ -1740,6 +1742,9 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int reg; u32 val; + assert_planes_disabled(dev_priv, pipe); + assert_sprites_disabled(dev_priv, pipe); + if (HAS_PCH_LPT(dev_priv->dev)) pch_transcoder = TRANSCODER_A; else