| Message ID | 1366070188-954-1-git-send-email-rodrigo.vivi@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Apr 15, 2013 at 08:56:28PM -0300, Rodrigo Vivi wrote: > This patch introduce Frame Buffer Compression (FBC) support for HSW. > It adds a new function haswell_enable_fbc to avoid getting > ironlake_enable_fbc messed with many IS_HASWELL checks. > > v2: Fixes from Ville. > * Fix Plane. FBC is tied to primary plane A in HSW > * Fix DPFC initial write to avoid let trash on the register. > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_pm.c | 46 ++++++++++++++++++++++++++++++++++++++++- > 3 files changed, 52 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 0cfc778..88fd6fb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -291,6 +291,7 @@ static const struct intel_device_info intel_haswell_m_info = { > GEN7_FEATURES, > .is_haswell = 1, > .is_mobile = 1, > + .has_fbc = 1, > }; > > static const struct pci_device_id pciidlist[] = { /* aka */ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5e91fbb..cb8e213 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -849,6 +849,12 @@ > #define SNB_CPU_FENCE_ENABLE (1<<29) > #define DPFC_CPU_FENCE_OFFSET 0x100104 > > +/* Framebuffer compression for Haswell */ > +#define HSW_FBC_RT_BASE 0x7020 > +#define HSW_FBC_RT_BASE_ADDR_SHIFT 12 > + > +#define HSW_DPFC_CTL_FENCE_EN (1<<28) > +#define HSW_DPFC_CTL_DISABLE_SLB_INIT (1<<15) > > /* > * GPIO regs > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 27f94cd..f3b35c4 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -253,6 +253,45 @@ static bool ironlake_fbc_enabled(struct drm_device *dev) > return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; > } > > +static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long interval) > +{ > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct drm_framebuffer *fb = crtc->fb; > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); > + struct drm_i915_gem_object *obj = intel_fb->obj; > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > + unsigned long stall_watermark = 200; > + > + /* FBC is tied to primary plane A in HSW */ > + if (intel_crtc->plane != PLANE_A) { > + dev_priv->no_fbc_reason = FBC_BAD_PLANE; > + return; > + } Already checked in intel_update_fbc() Otherwise looks fine. -Chris
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 0cfc778..88fd6fb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -291,6 +291,7 @@ static const struct intel_device_info intel_haswell_m_info = { GEN7_FEATURES, .is_haswell = 1, .is_mobile = 1, + .has_fbc = 1, }; static const struct pci_device_id pciidlist[] = { /* aka */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5e91fbb..cb8e213 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -849,6 +849,12 @@ #define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104 +/* Framebuffer compression for Haswell */ +#define HSW_FBC_RT_BASE 0x7020 +#define HSW_FBC_RT_BASE_ADDR_SHIFT 12 + +#define HSW_DPFC_CTL_FENCE_EN (1<<28) +#define HSW_DPFC_CTL_DISABLE_SLB_INIT (1<<15) /* * GPIO regs diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 27f94cd..f3b35c4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -253,6 +253,45 @@ static bool ironlake_fbc_enabled(struct drm_device *dev) return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; } +static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long interval) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_framebuffer *fb = crtc->fb; + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); + struct drm_i915_gem_object *obj = intel_fb->obj; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + unsigned long stall_watermark = 200; + + /* FBC is tied to primary plane A in HSW */ + if (intel_crtc->plane != PLANE_A) { + dev_priv->no_fbc_reason = FBC_BAD_PLANE; + return; + } + + I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | + (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | + (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); + I915_WRITE(HSW_FBC_RT_BASE, + obj->gtt_offset << HSW_FBC_RT_BASE_ADDR_SHIFT | + ILK_FBC_RT_VALID); + + I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X | + (HSW_DPFC_CTL_FENCE_EN | obj->fence_reg) | + HSW_DPFC_CTL_DISABLE_SLB_INIT); + + if (obj->fence_reg != I915_FENCE_REG_NONE) { + I915_WRITE(SNB_DPFC_CTL_SA, + SNB_CPU_FENCE_ENABLE | obj->fence_reg); + I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); + } else + I915_WRITE(SNB_DPFC_CTL_SA, ~SNB_CPU_FENCE_ENABLE); + + sandybridge_blit_fbc_update(dev); + + DRM_DEBUG_KMS("enabled fbc on plane A\n"); +} + bool intel_fbc_enabled(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4158,7 +4197,12 @@ void intel_init_pm(struct drm_device *dev) if (I915_HAS_FBC(dev)) { if (HAS_PCH_SPLIT(dev)) { dev_priv->display.fbc_enabled = ironlake_fbc_enabled; - dev_priv->display.enable_fbc = ironlake_enable_fbc; + if (IS_HASWELL(dev)) + dev_priv->display.enable_fbc = + haswell_enable_fbc; + else + dev_priv->display.enable_fbc = + ironlake_enable_fbc; dev_priv->display.disable_fbc = ironlake_disable_fbc; } else if (IS_GM45(dev)) { dev_priv->display.fbc_enabled = g4x_fbc_enabled;
This patch introduce Frame Buffer Compression (FBC) support for HSW. It adds a new function haswell_enable_fbc to avoid getting ironlake_enable_fbc messed with many IS_HASWELL checks. v2: Fixes from Ville. * Fix Plane. FBC is tied to primary plane A in HSW * Fix DPFC initial write to avoid let trash on the register. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_pm.c | 46 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 52 insertions(+), 1 deletion(-)