From patchwork Wed Apr 17 17:11:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 2455071 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id B49233FC64 for ; Wed, 17 Apr 2013 17:18:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9648CE66C9 for ; Wed, 17 Apr 2013 10:18:26 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C5C6E614E for ; Wed, 17 Apr 2013 10:12:27 -0700 (PDT) Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga102.ch.intel.com with ESMTP; 17 Apr 2013 10:12:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.87,494,1363158000"; d="scan'208";a="228439697" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.168]) by AZSMGA002.ch.intel.com with SMTP; 17 Apr 2013 10:12:05 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 17 Apr 2013 20:12:04 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 17 Apr 2013 20:11:59 +0300 Message-Id: <1366218721-17777-2-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1366218721-17777-1-git-send-email-ville.syrjala@linux.intel.com> References: <1366218721-17777-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915: Clarify DSPPOS/DSPSIZE and pipe selection for planes A/B X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Ville Syrjälä DSPPOS/DSPSIZE for planes A/B doesn't exist on Gen4+, so don't write them. Also the pipe selection for planes A and B is only relevant for Gen3 and earlier. Gen4 moved to fixed plane<->pipe mapping. Plane C is still movable between pipes on Gen4, but that fact is not relevant for the CRTC codepaths since we never use plane C as the CRTC plane. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fb88356..4f4a8d1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4719,8 +4719,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; - if (!IS_VALLEYVIEW(dev)) { - if (pipe == 0) + /* planes A/B are fixed to pipes A/B respectively on Gen4+ */ + if (INTEL_INFO(dev)->gen <= 3) { + if (pipe == PIPE_A) dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; else dspcntr |= DISPPLANE_SEL_PIPE_B; @@ -4733,11 +4734,15 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, /* pipesrc and dspsize control the size that is scaled from, * which should always be the user's requested size. + * + * DSPPOS/DSPSIZE for planes A/B only exist on Gen3 and earlier. */ - I915_WRITE(DSPSIZE(plane), - ((mode->vdisplay - 1) << 16) | - (mode->hdisplay - 1)); - I915_WRITE(DSPPOS(plane), 0); + if (INTEL_INFO(dev)->gen <= 3) { + I915_WRITE(DSPSIZE(plane), + ((mode->vdisplay - 1) << 16) | + (mode->hdisplay - 1)); + I915_WRITE(DSPPOS(plane), 0); + } i9xx_set_pipeconf(intel_crtc);