From patchwork Fri Apr 19 09:24:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2463871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 4A0403FD1A for ; Fri, 19 Apr 2013 09:30:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 445DEE67B6 for ; Fri, 19 Apr 2013 02:30:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f181.google.com (mail-ea0-f181.google.com [209.85.215.181]) by gabe.freedesktop.org (Postfix) with ESMTP id CB37DE66A5 for ; Fri, 19 Apr 2013 02:25:11 -0700 (PDT) Received: by mail-ea0-f181.google.com with SMTP id z10so1632345ead.12 for ; Fri, 19 Apr 2013 02:25:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=4vtRnbUjavIC2XhxFfSMgCWnhfYjGoe2JqYsoPVs+GI=; b=K3SLnu7HoDxCO1GPTxECZGTnt6u96jqXiaSYXwyHo4Mxj4pX+bR3BuAv9tqmxdzlQC 5rcjqA9uIpc2/85Um5pyfRq2/jwX4LH8aAt4XSNxRBaBXdM8Bc+K6x84aWkRfGv7btpv /Uq4+BNivQ3ONY15ZmPDWwPlIhedSIII6v4R8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=4vtRnbUjavIC2XhxFfSMgCWnhfYjGoe2JqYsoPVs+GI=; b=pDQmpyT10zzUvjhxoiacJt0vI8DCYSXd4W9Tf07A0YBVv9FajceRT91yykGs9Dh1U7 xUPpq9MQWrNuTnUg/AIvYmt8gLLkxTTXeiTIIOuXkVoJ0Oxjb43qUUUX0mTWhafDdxfu Zpvqy0k7rZd5VTckIXWBMQe6xXDZIAdA8bvoav4bQbgpIXRHnhZBcbbfxHLmml4IotTN 5bCcf9tE1KDaA2yxv8OY2S98ONRrbHZiQmf4gXf9JlrVQQ2tJjQLsu/IQL3mzkWOLF7Q 2QQ+zMgpSK4Co6qUrsbuU007OA+TCdLxt7wJgQDZob2uPkZ5oUnwWWTVUyh3BnCCjfN6 wTgQ== X-Received: by 10.15.31.197 with SMTP id y45mr39969384eeu.18.1366363510915; Fri, 19 Apr 2013 02:25:10 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id 8sm21552119eeg.15.2013.04.19.02.25.09 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 19 Apr 2013 02:25:09 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 19 Apr 2013 11:24:42 +0200 Message-Id: <1366363487-15926-11-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1366363487-15926-1-git-send-email-daniel.vetter@ffwll.ch> References: <1366363487-15926-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQk308Y05TMGY0Krnt30UqDAJNQrngFe91ptAf1ZGP0xdiSDJEb2lNnJzhkdPlH2LtHYZlSR Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 10/15] drm/i915: split up fdi_set_m_n into computation and hw setup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org And also move the computed m_n values into the pipe_config. This is a prep step to move the fdi state computation completely into the prepare phase of the modeset sequence. Which will allow us to handle fdi link bw constraints in a better way. Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++----------- drivers/gpu/drm/i915/intel_drv.h | 3 ++- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b7774c1..7abcd60 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5480,13 +5480,11 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, } } -static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) +static void ironlake_fdi_compute_config(struct intel_crtc *intel_crtc) { - struct drm_device *dev = crtc->dev; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct drm_device *dev = intel_crtc->base.dev; struct drm_display_mode *adjusted_mode = &intel_crtc->config.adjusted_mode; - struct intel_link_m_n m_n = {0}; int target_clock, lane, link_bw; /* FDI is a binary signal running at ~2.7GHz, encoding @@ -5511,9 +5509,7 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) if (intel_crtc->config.pixel_multiplier > 1) link_bw *= intel_crtc->config.pixel_multiplier; intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock, - link_bw, &m_n); - - intel_cpu_transcoder_set_m_n(intel_crtc, &m_n); + link_bw, &intel_crtc->config.fdi_m_n); } static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) @@ -5735,8 +5731,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, /* Note, this also computes intel_crtc->fdi_lanes which is used below in * ironlake_check_fdi_lanes. */ intel_crtc->config.fdi_lanes = 0; - if (intel_crtc->config.has_pch_encoder) - ironlake_fdi_set_m_n(crtc); + if (intel_crtc->config.has_pch_encoder) { + ironlake_fdi_compute_config(intel_crtc); + + intel_cpu_transcoder_set_m_n(intel_crtc, + &intel_crtc->config.fdi_m_n); + } fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc); @@ -5866,8 +5866,12 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); - if (intel_crtc->config.has_pch_encoder) - ironlake_fdi_set_m_n(crtc); + if (intel_crtc->config.has_pch_encoder) { + ironlake_fdi_compute_config(intel_crtc); + + intel_cpu_transcoder_set_m_n(intel_crtc, + &intel_crtc->config.fdi_m_n); + } haswell_set_pipeconf(crtc); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 179b42b..f40b43f 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -230,8 +230,9 @@ struct intel_crtc_config { /* Used by SDVO (and if we ever fix it, HDMI). */ unsigned pixel_multiplier; - /* FDI lanes used, only valid if has_pch_encoder is set. */ + /* FDI configuration, only valid if has_pch_encoder is set. */ int fdi_lanes; + struct intel_link_m_n fdi_m_n; }; struct intel_crtc {