From patchwork Wed Apr 24 00:33:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 2481741 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id EFC05DF2E5 for ; Wed, 24 Apr 2013 00:33:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7309E6124 for ; Tue, 23 Apr 2013 17:33:17 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from shiva.localdomain (unknown [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id E69CCE5C84 for ; Tue, 23 Apr 2013 17:33:08 -0700 (PDT) Received: by shiva.localdomain (Postfix, from userid 1005) id 449258865A; Wed, 24 Apr 2013 00:33:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on shiva.chad-versace.us X-Spam-Level: X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00, URIBL_BLOCKED autolearn=unavailable version=3.3.2 Received: from bolo_yeung.jf.intel.com (jfdmzpr01-ext.jf.intel.com [134.134.139.70]) by shiva.localdomain (Postfix) with ESMTPSA id E3501880AB; Wed, 24 Apr 2013 00:33:06 +0000 (UTC) From: Ben Widawsky To: intel-gfx@lists.freedesktop.org Date: Tue, 23 Apr 2013 17:33:02 -0700 Message-Id: <1366763582-7038-1-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.8.2.1 Cc: Ben Widawsky , kim.l.saw-chu@intel.com Subject: [Intel-gfx] [PATCH] Revert "drm/i915: Don't overclock on Haswell" X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This reverts commit fec46b5eff854df5647a9f4724e45dd33933855a. The latest version of our PM programming doc (which is WAY better than previous versions, and thanks for that) says something along the lines of, "On Haswell overclocking is no long achieved via mailbox registers." Which I misinterpreted as, the driver must done something different than it did on IVB, and SNB. It appears I jumped the gun, and that's all false. We've gotten some clarification, and it appears at least *reading* the overclocking information works in exactly the same manner. Cc: kim.l.saw-chu@intel.com Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2557926..5f912c6 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2685,7 +2685,7 @@ static void gen6_enable_rps(struct drm_device *dev) (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); - if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) { + if (!ret) { pcu_mbox = 0; ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */