From patchwork Tue Apr 30 12:01:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2504271 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id A66703FD85 for ; Tue, 30 Apr 2013 12:03:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B3913E6229 for ; Tue, 30 Apr 2013 05:03:21 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f176.google.com (mail-we0-f176.google.com [74.125.82.176]) by gabe.freedesktop.org (Postfix) with ESMTP id CA0F7E5D73 for ; Tue, 30 Apr 2013 05:01:57 -0700 (PDT) Received: by mail-we0-f176.google.com with SMTP id s10so342467wey.21 for ; Tue, 30 Apr 2013 05:01:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=x82HYVfPID5//RV3hbEOgaGT3Oj8bIih1FIPydxeeUs=; b=Mxt61nWRde0NfWWzATiEbzjpnxEkQiYRPv+WbyGpTsN9f5EMNw2vfWMliRp6O/k52d gD/B0gtZwM7THRM4z3BbEoKYpmDPXhwqjhX7KZgGPJH+QP7jp2F4tCtHjrfJuLpWG0Yr 2VZVAm3Vy5OvWjEg+WivD4k7g5KIy2ndAKOqw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=x82HYVfPID5//RV3hbEOgaGT3Oj8bIih1FIPydxeeUs=; b=fmLrmvjHUoXrq+mwKnPA3Oykpehhh5M/6DYDME3dioY9BL0vFFl2iBbmYevavyYVYL TQuELmTdDJnvehGLDcbLCDJV0SVrMG7wuUbe9+Gs0odz3gDLQiopyz3jCWU+y9wTjdMg ZY6CPD1c4nZun1o3Fmamg3UQxxxDxkowdnNgfror1SrHREv78P+C4ZXNvWo5BOk96Khp ndyZOu2zWh59QeHl/MyJhr1+sp7hVCp/sZ30TNHS70lZNL/uRT+Pa0K97FBJFnAdQpBb +tEx0tqXug1Kh3iEa6AKk6Mhq5T8bTx/Rl1h3HlGche4WXxkevAgVTNj2XSFBAjvE/jp 8QMw== X-Received: by 10.180.73.173 with SMTP id m13mr23808737wiv.27.1367323316926; Tue, 30 Apr 2013 05:01:56 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id k5sm28515344wiy.5.2013.04.30.05.01.55 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 30 Apr 2013 05:01:56 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 30 Apr 2013 14:01:41 +0200 Message-Id: <1367323306-13605-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1367323306-13605-1-git-send-email-daniel.vetter@ffwll.ch> References: <1367323306-13605-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmVxJutExWA+SAgNmiFJBnN2TBP1nmItMvdi/1pgbTkVRNJjDM4Y3FP80/PS8sfiwVEWPIr Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/7] drm/i915: move sdvo TV clock computation to intel_sdvo.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We have a very nice infrastructure for this now! Note that the multifunction sdvo support is pretty neatly broken: We completely ignore userspace's request for which connector to wire up with the encoder and just use whatever the last detect callback has seen. Not something I'll fix in this patch, but unfortunately something which is also broken in the DDI code ... v2: Don't call sdvo_tv_clock twice. Signed-off-by: Daniel Vetter Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 30 ------------------------------ drivers/gpu/drm/i915/intel_sdvo.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1128f83..f10f094 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4286,30 +4286,6 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) return refclk; } -static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc) -{ - unsigned dotclock = crtc->config.adjusted_mode.clock; - struct dpll *clock = &crtc->config.dpll; - - /* SDVO TV has fixed PLL values depend on its clock range, - this mirrors vbios setting. */ - if (dotclock >= 100000 && dotclock < 140500) { - clock->p1 = 2; - clock->p2 = 10; - clock->n = 3; - clock->m1 = 16; - clock->m2 = 8; - } else if (dotclock >= 140500 && dotclock <= 200000) { - clock->p1 = 1; - clock->p2 = 10; - clock->n = 6; - clock->m1 = 12; - clock->m2 = 8; - } - - crtc->config.clock_set = true; -} - static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) { return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2; @@ -4926,9 +4902,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, intel_crtc->config.dpll.p2 = clock.p2; } - if (is_sdvo && is_tv) - i9xx_adjust_sdvo_tv_clock(intel_crtc); - if (IS_GEN2(dev)) i8xx_update_pll(intel_crtc, adjusted_mode, has_reduced_clock ? &reduced_clock : NULL, @@ -5538,9 +5511,6 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc, reduced_clock); } - if (is_sdvo && is_tv) - i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc)); - return true; } diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index d154284..f6bf9fc 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1041,6 +1041,32 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, return true; } +static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config) +{ + unsigned dotclock = pipe_config->adjusted_mode.clock; + struct dpll *clock = &pipe_config->dpll; + + /* SDVO TV has fixed PLL values depend on its clock range, + this mirrors vbios setting. */ + if (dotclock >= 100000 && dotclock < 140500) { + clock->p1 = 2; + clock->p2 = 10; + clock->n = 3; + clock->m1 = 16; + clock->m2 = 8; + } else if (dotclock >= 140500 && dotclock <= 200000) { + clock->p1 = 1; + clock->p2 = 10; + clock->n = 6; + clock->m1 = 12; + clock->m2 = 8; + } else { + WARN(1, "SDVO TV clock out of range: %i\n", dotclock); + } + + pipe_config->clock_set = true; +} + static bool intel_sdvo_compute_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) { @@ -1097,6 +1123,10 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, if (intel_sdvo->color_range) pipe_config->limited_color_range = true; + /* Clock computation needs to happen after pixel multiplier. */ + if (intel_sdvo->is_tv) + i9xx_adjust_sdvo_tv_clock(pipe_config); + return true; }