From patchwork Wed May 1 16:03:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2508071 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 324053FD85 for ; Wed, 1 May 2013 16:04:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 08C96E62C9 for ; Wed, 1 May 2013 09:04:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) by gabe.freedesktop.org (Postfix) with ESMTP id 0234FE629F for ; Wed, 1 May 2013 09:03:39 -0700 (PDT) Received: by mail-wi0-f169.google.com with SMTP id h11so5373140wiv.4 for ; Wed, 01 May 2013 09:03:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=VKCU5R7FGHHPtv4zrCRmmN+iDt6hMBaE4zpi2LU/8fk=; b=OugkU1ABoG1/caDE2384NPzy8+db8Gd8p7Vntb/4zlM+KoVPdcVzabiwtjLAolG3S4 JXgyXt1aEriCwU3xPFE0PBrDZI38fGJ2/eoRkW0wItn6CyV0xa3aYiWFSLCKMUKE4uoV RDaXaxGFxuDEYSFvWDq5KRy7lk+cRrGcr+K34= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=VKCU5R7FGHHPtv4zrCRmmN+iDt6hMBaE4zpi2LU/8fk=; b=Es9t/5Qk7NQpa6GS36hEdXdWfck5AzBxSgj9A5BEFu3YNeD+Vcj3dX50OvWzUHVmKh 2Ag4BvejvFWS9d8zPqUSeD5pOlxD43NxkvTeyJAzTyIHBBdd3yhT8iJ5joCBHku5y1rb x5HJyogJdb9PKd5nHWo6JMMg7B+QwKuywJIm9TAsx2s4oXsVkpojOl1Dwgu9hvlug5nb qOWIbVUJ8yV/ortdrFsdIcljv6vwpZR0C03mM5N1/7SfWKPYgKRr0Y/2+XNptSc5hu4n uTO+3RuifPQtjSUeWeUZ9Qv+OVRG6FXcyPdwgBFrqPmGJnTKrpma8kVJqaKYaQBRUcJm niCQ== X-Received: by 10.180.87.170 with SMTP id az10mr3475960wib.3.1367424219317; Wed, 01 May 2013 09:03:39 -0700 (PDT) Received: from natalie.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id dj7sm32983360wib.6.2013.05.01.09.03.37 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 01 May 2013 09:03:38 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 1 May 2013 18:03:15 +0200 Message-Id: <1367424197-29664-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1367424197-29664-1-git-send-email-daniel.vetter@ffwll.ch> References: <1367424197-29664-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQkjPYzq9QztHYPrRPZgrQVyETGUBqVBj4WEL3YOXhj4/2SCF/oBOCQELlL+FSLgvk7H28Ix Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 3/5] drm/i915: make set_m_n functions static X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This is possible thanks to moving the m/n stuff into pipe_config. Unfortunately we need to move them a bit to avoid forward declarations. Signed-off-by: Daniel Vetter Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 68 ++++++++++++++++++------------------ drivers/gpu/drm/i915/intel_drv.h | 4 --- 2 files changed, 34 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2fe0913..3edda85 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4386,6 +4386,40 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); } +static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, + struct intel_link_m_n *m_n) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int pipe = crtc->pipe; + + I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n); + I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m); + I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n); +} + +static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, + struct intel_link_m_n *m_n) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int pipe = crtc->pipe; + enum transcoder transcoder = crtc->config.cpu_transcoder; + + if (INTEL_INFO(dev)->gen >= 5) { + I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); + I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); + I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); + } else { + I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n); + I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m); + I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n); + } +} + static void intel_dp_set_m_n(struct intel_crtc *crtc) { if (crtc->config.has_pch_encoder) @@ -5605,40 +5639,6 @@ int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) return bps / (link_bw * 8) + 1; } -void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, - struct intel_link_m_n *m_n) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - int pipe = crtc->pipe; - - I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n); - I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m); - I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n); -} - -void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, - struct intel_link_m_n *m_n) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - int pipe = crtc->pipe; - enum transcoder transcoder = crtc->config.cpu_transcoder; - - if (INTEL_INFO(dev)->gen >= 5) { - I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); - I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); - I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); - } else { - I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n); - I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m); - I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n); - } -} - static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) { return i9xx_dpll_compute_m(dpll) < factor * dpll->n; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index dfcf546..88890a3 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -719,10 +719,6 @@ extern void intel_init_clock_gating(struct drm_device *dev); extern void intel_write_eld(struct drm_encoder *encoder, struct drm_display_mode *mode); extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); -extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, - struct intel_link_m_n *m_n); -extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, - struct intel_link_m_n *m_n); extern void intel_prepare_ddi(struct drm_device *dev); extern void hsw_fdi_link_train(struct drm_crtc *crtc); extern void intel_ddi_init(struct drm_device *dev, enum port port);