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drm/i915: set proper DPIO post divider for VGA on VLV v2

Message ID 1367451586-3197-1-git-send-email-jbarnes@virtuousgeek.org (mailing list archive)
State New, archived
Headers show

Commit Message

Jesse Barnes May 1, 2013, 11:39 p.m. UTC 
It's only for the low rates that the divider value should be 0.

v2: remove unconditional write (Jesse)
    check for pixel rate properly (Jesse)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)
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Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6504337..92894b7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4425,9 +4425,16 @@  static void vlv_update_pll(struct intel_crtc *crtc)
 	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
 	mdiv |= ((bestn << DPIO_N_SHIFT));
 	mdiv |= (1 << DPIO_K_SHIFT);
-	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
-	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
-	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
+
+	/*
+	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
+	 * but we don't support that).
+	 */
+	DRM_ERROR("clock: %d\n", adjusted_mode->clock);
+	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) &&
+	    adjusted_mode->clock < 30000)
+		mdiv |= (DPIO_POST_DIV_DAC << DPIO_POST_DIV_SHIFT);
+	else
 		mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
 	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);