From patchwork Mon May 6 22:37:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2526571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id CBEDD3FC5A for ; Mon, 6 May 2013 22:38:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BEDF8E6179 for ; Mon, 6 May 2013 15:38:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f45.google.com (mail-yh0-f45.google.com [209.85.213.45]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FA93E6135 for ; Mon, 6 May 2013 15:37:51 -0700 (PDT) Received: by mail-yh0-f45.google.com with SMTP id b20so799722yha.4 for ; Mon, 06 May 2013 15:37:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=qbzIgTxG1pp9YVTfz83kM/tyWKHIdn4egOXVCvDNuxo=; b=KsI8dcjhpWPyGE2b+FKsKivwJ/irLkOPFr65Hf8yfl/5nZvLY+xYcl0wp4N/FjYOPk X6BsQ5iLgKiz4AE8gpgEK5HkSNUjhGmzPaIV7LNkNRYm22+X017hhsFZU2D04qHMvzKg 8GaRfg7oqmkaSfl/wea+lC6T7uj3S/fbLkws2SsCfR0cWMJQapf051pv6VeJA938QZqZ ra4H+Cc5ihoZc1M5jBKfPvWaNPSGlJvIIxnKrlfD+wEAu4RQqoHrm8j989oRhJ1os2O3 hPN8P07tGKpm+riKeN/HXpDE2wZnWxBkzSqj+KuUq8JXrPCSxX2uf3aUURa1Ak6MZy8H ItUg== X-Received: by 10.236.162.40 with SMTP id x28mr11766154yhk.202.1367879871039; Mon, 06 May 2013 15:37:51 -0700 (PDT) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPSA id d51sm1525907yho.14.2013.05.06.15.37.49 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 06 May 2013 15:37:50 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 6 May 2013 19:37:35 -0300 Message-Id: <1367879858-2163-3-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1367879858-2163-1-git-send-email-rodrigo.vivi@gmail.com> References: <1367879858-2163-1-git-send-email-rodrigo.vivi@gmail.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915: IVB FBC WaFbcDisableDpfcClockGating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Display register 42020h bit 9 must be set to 1b for the entire time that Frame Buffer Compression is enabled. v2: RMW to preserve other bits (by Ville) v3: Fix from Ville: sed &/| at RMW Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4661f9f..e9fb0ba 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -242,6 +242,12 @@ static void ironlake_disable_fbc(struct drm_device *dev) dpfc_ctl &= ~DPFC_CTL_EN; I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); + if (IS_IVYBRIDGE(dev)) + /* WaFbcDisableDpfcClockGating */ + I915_WRITE(ILK_DSPCLK_GATE_D, + I915_READ(ILK_DSPCLK_GATE_D) | + ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); + DRM_DEBUG_KMS("disabled FBC\n"); } } @@ -270,6 +276,11 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) /* WaFbcAsynchFlipDisableFbcQueue */ I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); + /* WaFbcDisableDpfcClockGating */ + I915_WRITE(ILK_DSPCLK_GATE_D, + I915_READ(ILK_DSPCLK_GATE_D) | + ILK_DPFCUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | obj->fence_reg); I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);