From patchwork Mon May 6 22:37:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2526581 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 8FF163FC5A for ; Mon, 6 May 2013 22:39:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7AB55E6170 for ; Mon, 6 May 2013 15:39:23 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ye0-f174.google.com (mail-ye0-f174.google.com [209.85.213.174]) by gabe.freedesktop.org (Postfix) with ESMTP id A4DDDE6141 for ; Mon, 6 May 2013 15:37:54 -0700 (PDT) Received: by mail-ye0-f174.google.com with SMTP id r13so783423yen.33 for ; Mon, 06 May 2013 15:37:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=5O/VtMao8IeKDc7+63/sgjuM2+tSVPtU8Tu7bMyBdnU=; b=meYY4jFsh99j2xjsjGOLFhvuSCxwp15qx8B3NE+SXI3sktnva12AfwDxeWX7A5H/2o XaNZICuvQb25YtmcM9isQjGSVv06MN6+rhQyY1EyPRmxD8MmKfaqXX03Q0Ml2wBK+R6N ChFAAvRmaI9W5dmVG3LwL0Nds6SDAT4C+snZvHxaUJqStuU2OtetAUuYIjp3/eTovE5J AEKjjilNIZIKanUPs2pUDm6tvxIH26AAAQCW2v/0uhFR4K7XVcZyClUdeq5GHlWAdb4r X0FYDzsS+3UKE2AziZgn2noiKoF38wYIefVO992i9BqvkcYgDN1CGe6DDm/oXw7Mmpq9 vSAQ== X-Received: by 10.236.198.136 with SMTP id v8mr17202929yhn.12.1367879874035; Mon, 06 May 2013 15:37:54 -0700 (PDT) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPSA id d51sm1525907yho.14.2013.05.06.15.37.51 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 06 May 2013 15:37:53 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 6 May 2013 19:37:36 -0300 Message-Id: <1367879858-2163-4-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1367879858-2163-1-git-send-email-rodrigo.vivi@gmail.com> References: <1367879858-2163-1-git-send-email-rodrigo.vivi@gmail.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Enable FBC at Haswell. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This patch introduce Frame Buffer Compression (FBC) support for HSW. FBC is tied to primary plane A in HSW. v2: Ville pointed out docs say FBC must be disabled before disabling the plane on HSW. v3: Really enabling it by default at HSW. Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/intel_display.c | 5 +++-- drivers/gpu/drm/i915/intel_pm.c | 21 ++++++++++++--------- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 319dc83..f11708a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -319,6 +319,7 @@ static const struct intel_device_info intel_haswell_m_info = { .is_mobile = 1, .has_ddi = 1, .has_fpga_dbg = 1, + .has_fbc = 1, }; static const struct pci_device_id pciidlist[] = { /* aka */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5491a58..8e5966e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3518,11 +3518,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) drm_vblank_off(dev, pipe); intel_crtc_update_cursor(crtc, false); - intel_disable_plane(dev_priv, plane, pipe); - + /* FBC must be disabled before disabling the plane on HSW. */ if (dev_priv->cfb_plane == plane) intel_disable_fbc(dev); + intel_disable_plane(dev_priv, plane, pipe); + if (intel_crtc->config.has_pch_encoder) intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); intel_disable_pipe(dev_priv, pipe); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e9fb0ba..5d40799 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -274,12 +274,14 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) IVB_DPFC_CTL_FENCE_EN | intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT); - /* WaFbcAsynchFlipDisableFbcQueue */ - I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); - /* WaFbcDisableDpfcClockGating */ - I915_WRITE(ILK_DSPCLK_GATE_D, - I915_READ(ILK_DSPCLK_GATE_D) | - ILK_DPFCUNIT_CLOCK_GATE_DISABLE); + if (IS_IVYBRIDGE(dev)) { + /* WaFbcAsynchFlipDisableFbcQueue */ + I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); + /* WaFbcDisableDpfcClockGating */ + I915_WRITE(ILK_DSPCLK_GATE_D, + I915_READ(ILK_DSPCLK_GATE_D) | + ILK_DPFCUNIT_CLOCK_GATE_DISABLE); + } I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | obj->fence_reg); @@ -476,7 +478,7 @@ void intel_update_fbc(struct drm_device *dev) if (enable_fbc < 0) { DRM_DEBUG_KMS("fbc set to per-chip default\n"); enable_fbc = 1; - if (INTEL_INFO(dev)->gen <= 7) + if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) enable_fbc = 0; } if (!enable_fbc) { @@ -497,7 +499,8 @@ void intel_update_fbc(struct drm_device *dev) dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; goto out_disable; } - if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { + if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) && + intel_crtc->plane != 0) { DRM_DEBUG_KMS("plane not 0, disabling compression\n"); dev_priv->no_fbc_reason = FBC_BAD_PLANE; goto out_disable; @@ -4456,7 +4459,7 @@ void intel_init_pm(struct drm_device *dev) if (I915_HAS_FBC(dev)) { if (HAS_PCH_SPLIT(dev)) { dev_priv->display.fbc_enabled = ironlake_fbc_enabled; - if (IS_IVYBRIDGE(dev)) + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) dev_priv->display.enable_fbc = gen7_enable_fbc; else