From patchwork Mon May 6 22:37:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2526591 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 9E5CE3FC5A for ; Mon, 6 May 2013 22:39:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9108FE612F for ; Mon, 6 May 2013 15:39:49 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gg0-f171.google.com (mail-gg0-f171.google.com [209.85.161.171]) by gabe.freedesktop.org (Postfix) with ESMTP id AAD91E6150 for ; Mon, 6 May 2013 15:37:58 -0700 (PDT) Received: by mail-gg0-f171.google.com with SMTP id r4so725987ggn.30 for ; Mon, 06 May 2013 15:37:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=ro9IJMTKj6ZBHbGd3Xysik4vTi3OrglrFjjDN/N4law=; b=gdUVGe5ap6uBq98jNSfhsyLqUQeCYMJKrixeHM3g7da8BwcLp+QKQ+8IIu9eOc07AI /5Gi05Qqf/BZkkvbGnBDitxMVlYFZMSf+72mVpPFnn6lH0Zg45J3EdHTwm9mVwI1QQza SZbI5paZPzjzFV+SGeChNJE7N2ez+u0QeVuTzYbgWZV1ESbCLF8QkT15cfwBC3qmnCZu TmE2tcMUwonM+Ojd2TpJcsR8nPuLgrOalNFXYA894QsQnnUjUBt6RO1VAPq50vAIh945 f5fLji+Tiiu5Kwmotu1FmYKFSfP/0RllRCtW7ox5JJnW35s72Lo804vHoVWCRqgUYe0x LyRg== X-Received: by 10.236.120.52 with SMTP id o40mr20343028yhh.58.1367879878169; Mon, 06 May 2013 15:37:58 -0700 (PDT) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPSA id d51sm1525907yho.14.2013.05.06.15.37.54 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 06 May 2013 15:37:57 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 6 May 2013 19:37:37 -0300 Message-Id: <1367879858-2163-5-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1367879858-2163-1-git-send-email-rodrigo.vivi@gmail.com> References: <1367879858-2163-1-git-send-email-rodrigo.vivi@gmail.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Display register 420B0h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a817b79..a17480e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -979,6 +979,13 @@ #define IVB_FBC_RT_BASE 0x7020 +#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 +#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 +#define HSW_BYPASS_FBC_QUEUE (1<<22) +#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ + _HSW_PIPE_SLICE_CHICKEN_1_A, + \ + _HSW_PIPE_SLICE_CHICKEN_1_B) + /* * GPIO regs */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5d40799..f074c0c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -281,6 +281,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) I915_WRITE(ILK_DSPCLK_GATE_D, I915_READ(ILK_DSPCLK_GATE_D) | ILK_DPFCUNIT_CLOCK_GATE_DISABLE); + } else { + /* WaFbcAsynchFlipDisableFbcQueue */ + I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), + HSW_BYPASS_FBC_QUEUE); } I915_WRITE(SNB_DPFC_CTL_SA,