From patchwork Thu May 9 17:20:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2544841 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id E5728DF24C for ; Thu, 9 May 2013 17:23:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B48A6E646F for ; Thu, 9 May 2013 10:23:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ye0-f174.google.com (mail-ye0-f174.google.com [209.85.213.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 2DC6EE5C59 for ; Thu, 9 May 2013 10:23:01 -0700 (PDT) Received: by mail-ye0-f174.google.com with SMTP id r13so721333yen.19 for ; Thu, 09 May 2013 10:23:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=bDCTnJ0aT+IOq6qQSDbWr8wI5QLXi339l+XCG4E3NmQ=; b=KG8GBJyu96yILGSiqmat1Jy33Ug3wXv5GKtucH8AD2RFhdZA2+R9NYygRztGo7BdqL sswI2EkRZn3pRxnJrmOoAkxOR4ZgMyScpT9va+2n2Z7N+H9deBEHIYcd9lFKX3YUIniX jfdOxZUlOLU/PAj3sxpETXSs24wqbZl3iTvxROGkiqsaxdSARaojzf8IUA4fagZP8qOc nv+Aax3RECKsT34TdXuFDRz6719W+XJ82VdcHz8RWmAKoz9sejFnSR2tnJgKmlssY8kG GHai0vG7Sh+AcV2SerJL9MwwA/BfY130unC8mR6LV4NTze/mV5hHB3Q+XRprZZT2/vBF gZTQ== X-Received: by 10.236.141.111 with SMTP id f75mr9524380yhj.204.1368120180729; Thu, 09 May 2013 10:23:00 -0700 (PDT) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPSA id d91sm1066874yhq.16.2013.05.09.10.22.03 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 09 May 2013 10:23:00 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Thu, 9 May 2013 14:20:50 -0300 Message-Id: <1368120050-3735-1-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1367879858-2163-6-git-send-email-rodrigo.vivi@gmail.com> References: <1367879858-2163-6-git-send-email-rodrigo.vivi@gmail.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: HSW FBC WaFbcDisableDpfcClockGating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Display register 46500h bit 23 must be set to 1b for the entire time that Frame Buffer Compression is enabled. v2: Ville suggested to enable it back when disabling fbc to avoid wasting power. v3: RMW to preserve other bits (by Ville) v4: Fix from Ville: sed &/| at RMW v5: Too far on sed. Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a17480e..40a59e5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -986,6 +986,9 @@ _HSW_PIPE_SLICE_CHICKEN_1_A, + \ _HSW_PIPE_SLICE_CHICKEN_1_B) +#define HSW_CLKGATE_DISABLE_PART_1 0x46500 +#define HSW_DPFC_GATING_DISABLE (1<<23) + /* * GPIO regs */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3f4bf58..aedf5da 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -248,6 +248,12 @@ static void ironlake_disable_fbc(struct drm_device *dev) I915_READ(ILK_DSPCLK_GATE_D) & ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); + if(IS_HASWELL(dev)) + /* WaFbcDisableDpfcClockGating */ + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, + I915_READ(HSW_CLKGATE_DISABLE_PART_1) & + ~HSW_DPFC_GATING_DISABLE); + DRM_DEBUG_KMS("disabled FBC\n"); } } @@ -285,6 +291,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) /* WaFbcAsynchFlipDisableFbcQueue */ I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), HSW_BYPASS_FBC_QUEUE); + /* WaFbcDisableDpfcClockGating */ + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, + I915_READ(HSW_CLKGATE_DISABLE_PART_1) | + HSW_DPFC_GATING_DISABLE); } I915_WRITE(SNB_DPFC_CTL_SA,