From patchwork Fri May 10 08:02:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2548591 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 9E26B3FC5A for ; Fri, 10 May 2013 08:03:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B831E5DEA for ; Fri, 10 May 2013 01:03:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f175.google.com (mail-ea0-f175.google.com [209.85.215.175]) by gabe.freedesktop.org (Postfix) with ESMTP id 6E241E6428 for ; Fri, 10 May 2013 01:03:04 -0700 (PDT) Received: by mail-ea0-f175.google.com with SMTP id q10so1992153eaj.6 for ; Fri, 10 May 2013 01:03:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=ynHpkqtXPiWu/S/FPjDCDJsNa4LL4DHqTUav24ef3L8=; b=RoZRT7jhjbcXQRxhugBNOJVN5OimGhtOHfQiRS5RcCi4533SK0oPOFxDricNnH6MWg daRORul3H/2bnKfEgyak5BZ7oa/eLFAlfpKmLhuJrfT2hvu/g+mdqLJcnDEk4N1VV/Cv VhMCcXdccCab5lKLTcCdFaoi7agYgSrsEzkQc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=ynHpkqtXPiWu/S/FPjDCDJsNa4LL4DHqTUav24ef3L8=; b=Lk4Kblw8vhSwdKiBrD99wXMYxfBxPiRVuu5rCmLxsKFSbz20CFJFrwb4f33hKMi8l8 /dXTMHzzsbZKIokyi7vuECCVn5T78t2MQx5xq+ySMFWuEFzY32Dq+5Txz4wUcCQbetpg uAsjkw38NFppKqFngSvzs3edNY10Z2lQRiRvxBhyt8OB0bEEyjQm080HGxQKimS/qyf8 DxHq+rC5F7zmro5RAb7URAHJmmE47Nff+2T3tiYzzlStUk8u+rBDBhOzKYHglhU/8SQa k9Esf2rPCA5XEO0mfXkBP4BFDv+bKWjJ8sUtfiN6GOr6FzxWht1A9TrZM9rE5z+SbDxq n8jg== X-Received: by 10.14.202.201 with SMTP id d49mr39012319eeo.1.1368172983421; Fri, 10 May 2013 01:03:03 -0700 (PDT) Received: from natalie.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id x41sm1865231eey.17.2013.05.10.01.03.01 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 10 May 2013 01:03:02 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 10 May 2013 10:02:55 +0200 Message-Id: <1368172975-23540-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1367611873-1315-1-git-send-email-daniel.vetter@ffwll.ch> References: <1367611873-1315-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQl4FegWldOYmH/Ob+4EAVNopGjQdUx2O0MhbMhDKBS7f6hN0jTvkvLmJ9X4SR5C3R+Rpf/s Cc: Daniel Vetter , Paulo Zanoni Subject: [Intel-gfx] [PATCH] drm/i915: hw state readout&check support for cpu_transcoder X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This allows us to drop a bunch of ugly hacks and finally implement what commit cc464b2a17c59adedbdc02cc54341d630354edc3 Author: Paulo Zanoni Date: Fri Jan 25 16:59:16 2013 -0200 drm/i915: set TRANSCODER_EDP even earlier tried to achieve, but that was reverted again in commit bba2181c49f1dddf8b592804a1b53cc1a3cf408a Author: Daniel Vetter Date: Fri Mar 22 10:53:40 2013 +0100 Revert "drm/i915: set TRANSCODER_EDP even earlier" Now we should always have a consistent cpu_transcoder in the pipe_config. v2: Fix up the code as spotted by Paulo: - read the register for real - assign the right pipes - break out if the hw state doesn't make sense Cc: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 4 ++ drivers/gpu/drm/i915/intel_display.c | 91 ++++++++++++++---------------------- 2 files changed, 38 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 8c4f2aa..baaf670 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1458,9 +1458,13 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) { int type = encoder->type; + int port = intel_ddi_get_encoder_port(encoder); WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); + if (port == PORT_A) + pipe_config->cpu_transcoder = TRANSCODER_EDP; + if (type == INTEL_OUTPUT_HDMI) return intel_hdmi_compute_config(encoder, pipe_config); else diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 219094f..6dcb3a6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3566,12 +3566,6 @@ static void ironlake_crtc_off(struct drm_crtc *crtc) static void haswell_crtc_off(struct drm_crtc *crtc) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - /* Stop saying we're using TRANSCODER_EDP because some other CRTC might - * start using it. */ - intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; - intel_ddi_put_crtc_pll(crtc); } @@ -5038,6 +5032,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; uint32_t tmp; + pipe_config->cpu_transcoder = crtc->pipe; + tmp = I915_READ(PIPECONF(crtc->pipe)); if (!(tmp & PIPECONF_ENABLE)) return false; @@ -5789,8 +5785,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); - intel_crtc->config.cpu_transcoder = pipe; - ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, &has_reduced_clock, &reduced_clock); if (!ok) { @@ -5913,6 +5907,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; uint32_t tmp; + pipe_config->cpu_transcoder = crtc->pipe; + tmp = I915_READ(PIPECONF(crtc->pipe)); if (!(tmp & PIPECONF_ENABLE)) return false; @@ -5987,11 +5983,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, num_connectors++; } - if (is_cpu_edp) - intel_crtc->config.cpu_transcoder = TRANSCODER_EDP; - else - intel_crtc->config.cpu_transcoder = pipe; - /* We are not sure yet this won't happen. */ WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); @@ -6047,14 +6038,37 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; uint32_t tmp; + pipe_config->cpu_transcoder = crtc->pipe; + tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); + if (tmp & TRANS_DDI_FUNC_ENABLE) { + enum pipe trans_edp_pipe; + switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { + default: + WARN(1, "unknown pipe linked to edp transcoder\n"); + break; + case TRANS_DDI_EDP_INPUT_A_ONOFF: + case TRANS_DDI_EDP_INPUT_A_ON: + trans_edp_pipe = PIPE_A; + break; + case TRANS_DDI_EDP_INPUT_B_ONOFF: + trans_edp_pipe = PIPE_B; + break; + case TRANS_DDI_EDP_INPUT_C_ONOFF: + trans_edp_pipe = PIPE_C; + break; + } + + if (trans_edp_pipe == crtc->pipe) + pipe_config->cpu_transcoder = TRANSCODER_EDP; + } + if (!intel_display_power_enabled(dev, - POWER_DOMAIN_TRANSCODER(cpu_transcoder))) + POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) return false; - tmp = I915_READ(PIPECONF(cpu_transcoder)); + tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); if (!(tmp & PIPECONF_ENABLE)) return false; @@ -6063,7 +6077,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, * DDI E. So just check whether this pipe is wired to DDI E and whether * the PCH transcoder is on. */ - tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { pipe_config->has_pch_encoder = true; @@ -7814,6 +7828,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, drm_mode_copy(&pipe_config->adjusted_mode, mode); drm_mode_copy(&pipe_config->requested_mode, mode); + pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe; plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config); if (plane_bpp < 0) @@ -8063,6 +8078,8 @@ intel_pipe_config_compare(struct intel_crtc_config *current_config, return false; \ } + PIPE_CONF_CHECK_I(cpu_transcoder); + PIPE_CONF_CHECK_I(has_pch_encoder); PIPE_CONF_CHECK_I(fdi_lanes); PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); @@ -8206,7 +8223,6 @@ intel_modeset_check_state(struct drm_device *dev) "crtc's computed enabled state doesn't match tracked enabled state " "(expected %i, found %i)\n", enabled, crtc->base.enabled); - pipe_config.cpu_transcoder = crtc->config.cpu_transcoder; active = dev_priv->display.get_pipe_config(crtc, &pipe_config); WARN(crtc->active != active, @@ -8269,12 +8285,10 @@ static int __intel_set_mode(struct drm_crtc *crtc, * to set it here already despite that we pass it down the callchain. */ if (modeset_pipes) { - enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder; crtc->mode = *mode; /* mode_set/enable/disable functions rely on a correct pipe * config. */ to_intel_crtc(crtc)->config = *pipe_config; - to_intel_crtc(crtc)->config.cpu_transcoder = tmp; } /* Only after disabling all output pipelines that will be changed can we @@ -8685,7 +8699,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) /* Swap pipes & planes for FBC on pre-965 */ intel_crtc->pipe = pipe; intel_crtc->plane = pipe; - intel_crtc->config.cpu_transcoder = pipe; if (IS_MOBILE(dev) && IS_GEN3(dev)) { DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); intel_crtc->plane = !pipe; @@ -9557,50 +9570,14 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, { struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe; - u32 tmp; struct drm_plane *plane; struct intel_crtc *crtc; struct intel_encoder *encoder; struct intel_connector *connector; - if (HAS_DDI(dev)) { - tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); - - if (tmp & TRANS_DDI_FUNC_ENABLE) { - switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { - case TRANS_DDI_EDP_INPUT_A_ON: - case TRANS_DDI_EDP_INPUT_A_ONOFF: - pipe = PIPE_A; - break; - case TRANS_DDI_EDP_INPUT_B_ONOFF: - pipe = PIPE_B; - break; - case TRANS_DDI_EDP_INPUT_C_ONOFF: - pipe = PIPE_C; - break; - default: - /* A bogus value has been programmed, disable - * the transcoder */ - WARN(1, "Bogus eDP source %08x\n", tmp); - intel_ddi_disable_transcoder_func(dev_priv, - TRANSCODER_EDP); - goto setup_pipes; - } - - crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); - crtc->config.cpu_transcoder = TRANSCODER_EDP; - - DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n", - pipe_name(pipe)); - } - } - -setup_pipes: list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { - enum transcoder tmp = crtc->config.cpu_transcoder; memset(&crtc->config, 0, sizeof(crtc->config)); - crtc->config.cpu_transcoder = tmp; crtc->active = dev_priv->display.get_pipe_config(crtc, &crtc->config);