[2/2,libdrm] intel: Adding more reserved PCI IDs for Haswell.

Commit Message

Rodrigo Vivi May 13, 2013, 8:48 p.m. UTC

At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.

References: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi <[e-mail]>
---
 intel/intel_chipset.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 51 insertions(+), 3 deletions(-)

Patch

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 3350def..aeb439e 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -97,6 +97,12 @@ 
 #define PCI_CHIP_HASWELL_S_GT1		0x040A /* Server */
 #define PCI_CHIP_HASWELL_S_GT2		0x041A
 #define PCI_CHIP_HASWELL_S_GT3		0x042A
+#define PCI_CHIP_HASWELL_B_GT1		0x040B /* Reserved */
+#define PCI_CHIP_HASWELL_B_GT2		0x041B
+#define PCI_CHIP_HASWELL_B_GT3		0x042B
+#define PCI_CHIP_HASWELL_E_GT1		0x040E /* Reserved */
+#define PCI_CHIP_HASWELL_E_GT2		0x041E
+#define PCI_CHIP_HASWELL_E_GT3		0x042E
 #define PCI_CHIP_HASWELL_SDV_GT1	0x0C02 /* Desktop */
 #define PCI_CHIP_HASWELL_SDV_GT2	0x0C12
 #define PCI_CHIP_HASWELL_SDV_GT3	0x0C22
@@ -106,6 +112,12 @@ 
 #define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A /* Server */
 #define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
 #define PCI_CHIP_HASWELL_SDV_S_GT3	0x0C2A
+#define PCI_CHIP_HASWELL_SDV_B_GT1	0x0C0B /* Reserved */
+#define PCI_CHIP_HASWELL_SDV_B_GT2	0x0C1B
+#define PCI_CHIP_HASWELL_SDV_B_GT3	0x0C2B
+#define PCI_CHIP_HASWELL_SDV_E_GT1	0x0C0E /* Reserved */
+#define PCI_CHIP_HASWELL_SDV_E_GT2	0x0C1E
+#define PCI_CHIP_HASWELL_SDV_E_GT3	0x0C2E
 #define PCI_CHIP_HASWELL_ULT_GT1	0x0A02 /* Desktop */
 #define PCI_CHIP_HASWELL_ULT_GT2	0x0A12
 #define PCI_CHIP_HASWELL_ULT_GT3	0x0A22
@@ -115,6 +127,12 @@ 
 #define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A /* Server */
 #define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
 #define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
+#define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B /* Reserved */
+#define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
+#define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
+#define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E /* Reserved */
+#define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
+#define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
 #define PCI_CHIP_HASWELL_CRW_GT1	0x0D02 /* Desktop */
 #define PCI_CHIP_HASWELL_CRW_GT2	0x0D12
 #define PCI_CHIP_HASWELL_CRW_GT3	0x0D22
@@ -124,6 +142,12 @@ 
 #define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A /* Server */
 #define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
 #define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
+#define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B /* Reserved */
+#define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
+#define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
+#define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
+#define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
+#define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
 
 #define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
 #define PCI_CHIP_VALLEYVIEW_1		0x0f31
@@ -210,39 +234,63 @@ 
 #define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
+				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
+				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
+				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
+				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
+				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
+				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1)
+				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
+				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
+				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
 #define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
+				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
+				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
+				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
+				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
+				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
+				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
+				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
 #define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
+				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
+				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
+				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
+				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
+				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
+				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
+				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
+				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
 
 #define IS_HASWELL(devid)	(IS_HSW_GT1(devid) || \
 				 IS_HSW_GT2(devid) || \